The increase in the density of transistors in integrated circuits
leads to less reliable hardware and higher likelihood for transient
errors. While the transistor density gains are utilized to put multiple
cores on a single chip, energy limitations will require a heterogenous
power distribution among the increasing number of cores.
In my doctoral work, I investigate how software transactional memory
can enhance the robustness and performance of applications that execute
on such hardware. The main covered aspects are (1) progress guarantees
for fairness among threads in the presence of errors, (2) fault tolerance
for transient errors and other symptoms without redundant execution, (3)
reducing the latency of operations using asymmetric levels of
instrumentation and (4) throughput improvement by exploiting heterogeneous
frequencies of cores.
For my status presentation, I will outline the related work in the
field as well as my contributions and plans for the remainder of my
work.
