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29.
11.
2019
RISC-V - The Free and Open RISC Instruction Set Architecture
Georg Kotheimer
TU Dresden
Hauptseminar-Vortrag
RISC-V is a free and open instruction set architecture developed
according to Reduced Instruction Set Computer (RISC) principles.
Special attention was paid to simplicity and extensibility in order to
keep the entry hurdle for research and teaching low on the one hand and
to cover small and cost-efficient embedded systems as well as high
performance computers on the other hand.
This presentation gives a brief introduction to RISC-V, followed by an
overview of the hardware/software ecosystem and a closer look at the
privileged architecture described in the RISC-V specification.
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