|Betriebssysteme · Institut für Systemarchitektur · Fakultät Informatik · TU Dresden|
10. 05. 2019
Building Enzian: a research computer
Academic research in rack-scale and datacenter computing today is hamstrung by lack of hardware. Cloud providers and hardware vendors build custom accelerators, interconnects, and networks for commercially important workloads, but university researchers are stuck with commodity, off-the-shelf parts.
Enzian is a series research computer being developed at ETH Zurich (in collaboration with Cavium and Xilinx) to tackle this problem. By providing a powerful and flexible platform for computer systems research, Enzian aims to enable more relevant and far-reaching work on future compute platforms.
An Enzian board consists of a server-class ARMv8 SoC tightly coupled and cache-coherent with a large FPGA (eliminating PCIe), with about 0.5 TB DDR4 and nearly 500 Gb/s of network I/O either to the CPU (over Ethernet) or directly to the FPGA (potentially over custom protocols). Enzian runs both Barrelfish and Linux operating systems. Many Enzian boards can be connected in a rack-scale machine (either with or without a discrete switch) and the design is intended to allow many different research use-cases: zero-overhead run-time verification of software invariants, novel interconnect protocols for remote memory access, hardware enforcement of access control in a large machine, high-performance streaming analytics using a combination of software and configurable hardware, and much more.
10. 05. 2019
A New System Architecture for Heterogeneous Compute Units
Dissertationsverteidigung (APB 1004 9:45)
The ongoing trend to more heterogeneity forces us to rethink the design of systems. In this talk, I will present a new system architecture that considers heterogeneous compute units (general-purpose cores with different instruction sets, DSPs, FPGAs, fixed-function accelerators, etc.) from the beginning instead of as an afterthought. The goal is to integrate all compute units (CUs) as first-class citizens, enabling 1) isolation and secure communication between all types of CUs, 2) direct interactions of all CUs to remove the conventional CPU from the critical path, 3) access to OS services such as file systems and network stacks for all CUs, and 4) context switching support on all CUs.
In contrast to existing approaches that try to use existing hardware in the best possible way, my work uses a hardware/operating system co-design based on two key ideas: 1) introduce a new hardware component next to each CU used by the OS as the CUs' common interface and 2) let the OS kernel control applications remotely from a different CU. In my talk, I will show how this approach allows to support arbitrary CUs as aforementioned first-class citizens, ranging from fixed-function accelerators to complex general-purpose cores.
25. Jun 2020
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