ata_channel.hpp

#if !defined(__ATA_CHANNEL_HPP__)
#define __ATA_CHANNEL_HPP__

//
// local includes
//
#include "ata_drive.hpp"

struct ata_channel : public iospace_handler, public mmio_handler, private noncopyable
{
  protected:
    const string channel_name;

    l4_gpa_t command_base,

             control_base;

    ata_drive *drives[2];

    uint8_t current_drive;

  public:
    //
    // constructor & destructor
    //
    inline ata_channel(machine_base &machine, const string &channel_name, ata_drive *drives[2])
        : channel_name(channel_name), command_base(0), control_base(0), current_drive(0)
    {
        // we always need a drive to handle the protocol correctly
        this->drives[0]=drives[0] ? drives[0] : new ata_drive(machine);
        this->drives[0]->set_drive_name_index(channel_name + " master", 0);
        this->drives[1]=drives[1] ? drives[1] : new ata_drive(machine);
        this->drives[1]->set_drive_name_index(channel_name + " slave", 1);
    }

    virtual inline ~ata_channel(void)
    {
        delete drives[1];
        delete drives[0];
    }

    //
    // iospace_handler: override I/O space access handlers
    //
    virtual inline uint32_t read_ioport(l4_port_t port, access_size access_size)
    {
        static const char *type="port";
        return read_blocks<type, l4_port_t>(port, access_size);
    }

    virtual inline int write_ioport(l4_port_t port, uint32_t data, access_size access_size)
    {
        static const char *type="port";
        return write_blocks<type, l4_port_t>(port, data, access_size);
    }

    //
    // mmio_handler: override read_mmio/write_mmio & I/O memory (un)map functions
    //
    virtual inline l4_umword_t read_mmio(l4_gpa_t address, access_size access_size)
    {
        static const char *type="address";
        return read_blocks<type, l4_gpa_t>(address, access_size);
    }

    virtual inline int write_mmio(l4_gpa_t address, l4_umword_t data, access_size access_size)
    {
        static const char *type="address";
        return write_blocks<type, l4_gpa_t>(address, data, access_size);
    }

    virtual inline l4_hva_t map_mmio_region(int flags, l4_gpa_t base, l4_gpa_t size=1)
    {
        // dummy. should not be called.
        return 0;
    }

    virtual inline int unmap_mmio_region(l4_gpa_t base, l4_gpa_t size=1)
    {
        // dummy. should not be called.
        return -L4_ENOTSUPP;
    }

    //
    // channel management functions
    //
    inline const char *name(void) const
    {
        return channel_name.c_str();
    }

    inline int reset(void)
    {
        return drives[0]->reset() | drives[1]->reset();
    }

    //
    // resources functions
    //
    inline void locate_registers(const l4_gpa_t command_base=0, const l4_gpa_t control_base=0)
    {
        this->command_base=command_base;
        this->control_base=control_base;
    }

    inline void set_irq(const l4_irq_t irq)
    {
        // the controller requests an IRQ, so always (try to) use what is set
        drives[0]->set_irq(irq);
        drives[1]->set_irq(irq);
    }

    inline void assert_irq_if_enabled(void)
    {
        drives[current_drive]->assert_irq_if_enabled();
    }

    //
    // DMA read/write functions:
    //     read_write as the IDE controller was programed
    //
    inline int read_write_DMA(uint8_t read_write, l4_gpa_t PRD_base)
    {
        return drives[current_drive]->read_write_DMA(read_write, PRD_base);
    }

  protected:
    //
    // read & write command & control block functions
    //
    template <const char *&AddressTypeC, typename AddressT>
    inline l4_umword_t read_blocks(AddressT address, access_size access_size)
    {
        if (command_base && (address >= command_base) && (address < command_base + sizeof(ata_command_block)))
            return drives[current_drive]->read_command_block(address - command_base, access_size);

        if (control_base && (address >= control_base) && (address < control_base + sizeof(ata_control_block)))
            return drives[current_drive]->read_control_block(address - control_base, access_size);

        logd(L4VMM_DEBUG_ATA >= 2, L4VMM_ERROR": %s:\n  invalid read from %s %s [%d]\n",
             name(), AddressTypeC, format_hex<AddressT>(address).c_str(), access_size());
        return iospace_handler::INVALID;
    }

    template <const char *&AddressTypeC, typename AddressT>
    inline int write_blocks(AddressT address, l4_umword_t data, access_size access_size)
    {
        if (command_base && (address >= command_base) && (address < command_base + sizeof(ata_command_block))) {
            //
            // check for device register (device bit) & switch drive
            //
            const ata_command_block::offset_t offset=address - command_base;
            if (ata_command_block::is_device(offset))
                current_drive=(data >> ata_command_block::DEVICE_REGISTER_DEVICE_BIT) & 0x01;

            return drives[current_drive]->write_command_block(offset, data, access_size);
        }

        if (control_base && (address >= control_base) && (address < control_base + sizeof(ata_control_block)))
            return drives[current_drive]->write_control_block(address - control_base, data, access_size);

        logd(L4VMM_DEBUG_ATA >= 2, L4VMM_ERROR": %s:\n  invalid write to %s %s [%d]\n",
             name(), AddressTypeC, format_hex<AddressT>(address).c_str(), access_size());
        return -L4_EINVAL;
    }
};

#endif

// ***** end of source ***** //