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i440fx_config_address.hpp

00001 #if !defined(__I440FX_CONFIG_ADDRESS_HPP__)
00002 #define __I440FX_CONFIG_ADDRESS_HPP__
00003 
00004 //
00005 // local includes
00006 //
00007 #include "core/machine/pci/pci_devfn.hpp"
00008 
00012 struct __packed(i440fx_config_address)
00013 {
00014     union
00015     {
00016         le_uint32_t raw;
00017 
00018         struct __packed()
00019         {
00020           #if LITTLE_ENDIAN_BITFIELD
00021             unsigned reserved0_1     : 2;       // bit 0-1
00022             unsigned register_number : 6;       // bit 2-7
00023             unsigned function_number : 3;       // bit 8-10
00024             unsigned device_number   : 5;       // bit 11-15
00025             unsigned bus_number      : 8;       // bit 16-23
00026             unsigned reserved24_30   : 7;       // bit 24-30
00027             unsigned enable          : 1;       // bit 31
00028           #elif BIG_ENDIAN_BITFIELD
00029             unsigned register_number : 6;       // bit 2-7
00030             unsigned reserved0_1     : 2;       // bit 0-1
00031             unsigned device_number   : 5;       // bit 11-15
00032             unsigned function_number : 3;       // bit 8-10
00033             unsigned bus_number      : 8;       // bit 16-23
00034             unsigned enable          : 1;       // bit 31
00035             unsigned reserved24_30   : 7;       // bit 24-30
00036           #else
00037             #error unknown bitfield order. fix this.
00038           #endif
00039         };
00040     };
00041 
00042     //
00043     // query functions
00044     //
00045     inline bool is_bus0_access(void) const
00046     {
00047         return (raw & 0x80ff0000) == 0x80000000;
00048     }
00049 
00050     inline bool is_bridge_access(void) const
00051     {
00052         // the bridge itself responds to requests for bus 0, device 0, function 0
00053         return (raw & 0x80ffff00) == 0x80000000;
00054     }
00055 
00056     inline bool is_device_access(void) const
00057     {
00058         return is_bus0_access() && ((raw & 0x0000ff00) != 0x00000000);
00059     }
00060 
00061     inline pci_devfn devfn(void) const
00062     {
00063         return pci_devfn((raw >> 8) & 0xff);
00064     }
00065 
00066     inline uint32_t register_offset(void) const
00067     {
00068         return raw & 0x000000fc;
00069     }
00070 
00071     //
00072     // read/write as little-endian (typecast/assignment convert to/from CPU endianess)
00073     //
00074     inline uint32_t read_le(void) const
00075     {
00076         return raw.bits;
00077     }
00078 
00079     inline void write_le(const uint32_t value)
00080     {
00081         raw.bits=value;
00082     }
00083 
00084     ACCESS_FUNCTORS(i440fx_config_address&, uint32_t, raw)
00085     NUMERIC_ACCESS_OPERATORS(i440fx_config_address&, uint32_t, raw)
00086     NUMERIC_ACCESS_OPERATORS(i440fx_config_address&, le_uint32_t, raw)
00087     INCREMENT_OPERATORS(i440fx_config_address, raw)
00088 };
00089 
00090 static_assert(sizeof(i440fx_config_address) == 4, "i440fx_config_address's size must be 4");
00091 
00092 #endif
00093 
00094 // ***** end of source ***** //
00095 

L4vmm Reference Manual, written by Mario Schwalbe  © 2006-2008