i440fx_config_space.hpp

#if !defined(__I440FX_CONFIG_SPACE_HPP__)
#define __I440FX_CONFIG_SPACE_HPP__

//
// local includes
//
#include "core/machine/pci/pci_config_space.hpp"

struct __packed(i440fx_config_space) : public pci_config_header64
{
    static const uint8_t MAX_PAM_REGISTERS = 7;

    //
    // these registers are defined but useless for software emulation
    //
    uint8_t unused40_58[0x58-sizeof(pci_config_header64)+1];

    //
    // Programmable Attribute Map (PAM) registers at offsets: 0x59 - 0x5f
    //
    union pam
    {
        uint8_t raw;

        struct __packed()
        {
          #if LITTLE_ENDIAN_BITFIELD
            unsigned enable_read        : 1;    // bit 0
            unsigned enable_write       : 1;    // bit 1
            unsigned reserved2_3        : 2;    // bit 2-3
            unsigned enable_read2       : 1;    // bit 4
            unsigned enable_write2      : 1;    // bit 5
            unsigned reserved6_7        : 2;    // bit 6-7
          #elif BIG_ENDIAN_BITFIELD
            unsigned reserved6_7        : 2;    // bit 6-7
            unsigned enable_write2      : 1;    // bit 5
            unsigned enable_read2       : 1;    // bit 4
            unsigned reserved2_3        : 2;    // bit 2-3
            unsigned enable_write       : 1;    // bit 1
            unsigned enable_read        : 1;    // bit 0
          #else
            #error unknown bitfield order. fix this.
          #endif
        };

        ACCESS_FUNCTORS(pam&, uint8_t, raw)
        NUMERIC_ACCESS_OPERATORS(pam&, uint8_t, raw)
        INCREMENT_OPERATORS(pam, raw)
    } pam[7];

    //
    // reserved or useless
    //
    uint8_t unused60_71[0x71-0x5f];

    //
    // System Management RAM (SMRAM) control register at offset: 0x72
    //
    union smram
    {
        uint8_t raw;

        struct __packed()
        {
          #if LITTLE_ENDIAN_BITFIELD
            unsigned space_base_segment : 3;    // bit 0-2
            unsigned enable             : 1;    // bit 3
            unsigned lock_space         : 1;    // bit 4
            unsigned close_space        : 1;    // bit 5
            unsigned open_space         : 1;    // bit 6
            unsigned reserved7          : 1;    // bit 7
          #elif BIG_ENDIAN_BITFIELD
            unsigned reserved7          : 1;    // bit 7
            unsigned open_space         : 1;    // bit 6
            unsigned close_space        : 1;    // bit 5
            unsigned lock_space         : 1;    // bit 4
            unsigned enable             : 1;    // bit 3
            unsigned space_base_segment : 3;    // bit 0-2
          #else
            #error unknown bitfield order. fix this.
          #endif
        };

        ACCESS_FUNCTORS(smram&, uint8_t, raw)
        NUMERIC_ACCESS_OPERATORS(smram&, uint8_t, raw)
        INCREMENT_OPERATORS(smram, raw)
    } smram;

    //
    // dito: reserved or useless
    //
    uint8_t unused73_ff[0xff-0x72];

    //
    // constructor
    //
    i440fx_config_space(void)
    {
        memset(this, 0, static_unsigned_min<sizeof(i440fx_config_space), 256>::value);
    }
};

static_assert(sizeof(i440fx_config_space) == 256, "i440fx_config_space's size must be 256");

#endif

// ***** end of source ***** //