in_out.hpp

#if !defined(__IN_OUT_HPP__)
#define __IN_OUT_HPP__

//
// x86 in{b,w,l} emulation
//
template <typename WordT>
inline int x86_in(x86_machine &machine, x86_context &ctx, const l4_port_t port)
{
    const access_size access_size=sizeof(WordT);
    logd(L4VMM_DEBUG_X86 >= 4, "  reading %s from port "l4_port_fmt" [%d]\n",
         access_size.string(), port, access_size());

    // merge read bits with old register content
    const l4_umword_t mask=access_size.mask();
    ctx.eax()=(ctx.eax() & ~mask) | machine.template read_virtual_ioport<WordT>(port);

    logd(L4VMM_DEBUG_X86 >= 3, "  read %s %s from port "l4_port_fmt" [%d]\n",
         access_size.string(), format_hex<WordT>(ctx.eax(), access_size*2).c_str(), port, access_size());
    return 0;
}

//
// x86 out{b,w,l} emulation
//
template <typename WordT>
inline int x86_out(x86_machine &machine, x86_context &ctx, const l4_port_t port)
{
    const access_size access_size=sizeof(WordT);
    logd(L4VMM_DEBUG_X86 >= 3, "  writing %s %s to port "l4_port_fmt" [%d]\n",
         access_size.string(), format_hex<WordT>(ctx.eax(), access_size*2).c_str(), port, access_size());

    machine.template write_virtual_ioport<WordT>(port, ctx.eax());
    return 0;
}

//
// x86 ins{b,w,l} emulation
//
template <typename WordT>
inline int x86_ins(x86_machine &machine, x86_context &ctx, bool rep=true)
{
    const access_size access_size=sizeof(WordT);
    const l4_port_t port=ctx.edx() & 0xffff;
    const short delta=(ctx.eflags() & (1<<10)) ? -1 : 1;
    WordT *p=reinterpret_cast<WordT *>(ctx.edi());

    if (likely(rep)) {
        logd(L4VMM_DEBUG_X86 >= 3, "  reading %ld %ss from port "l4_port_fmt" to "l4_gva_fmt"\n",
             ctx.ecx(), access_size.string(), port, ctx.edi());

        ctx.edi()+=access_size * delta * ctx.ecx();
        for (; ctx.ecx() > 0; ctx.ecx()--, p+=delta)
            *p=machine.template read_virtual_ioport<WordT>(port);
    }
    else {
        logd(L4VMM_DEBUG_X86 >= 3, "  reading 1 %s from port "l4_port_fmt" to "l4_gva_fmt"\n",
             access_size.string(), port, ctx.edi());

        ctx.edi()+=access_size * delta;
        *p=machine.template read_virtual_ioport<WordT>(port);
    }

    return 0;
}

//
// x86 outs{b,w,l} emulation
//
template <typename WordT>
inline int x86_outs(x86_machine &machine, x86_context &ctx, bool rep=true)
{
    const access_size access_size=sizeof(WordT);
    const l4_port_t port=ctx.edx() & 0xffff;
    const short delta=(ctx.eflags() & (1<<10)) ? -1 : 1;
    const WordT *p=reinterpret_cast<const WordT *>(ctx.esi());

    if (likely(rep)) {
        logd(L4VMM_DEBUG_X86 >= 3, "  writing %ld %ss from "l4_gva_fmt" to port "l4_port_fmt"\n",
             ctx.ecx(), access_size.string(), ctx.esi(), port);

        ctx.esi()+=access_size * delta * ctx.ecx();
        for (; ctx.ecx() > 0; ctx.ecx()--, p+=delta)
            machine.template write_virtual_ioport<WordT>(port, *p);
    }
    else {
        logd(L4VMM_DEBUG_X86 >= 3, "  writing 1 %s from "l4_gva_fmt" to port "l4_port_fmt"\n",
             access_size.string(), ctx.esi(), port);

        ctx.esi()+=access_size * delta;
        machine.template write_virtual_ioport<WordT>(port, *p);
    }

    return 0;
}

#endif

// ***** end of source ***** //