io_page_fault_udis86.hpp

#if !defined(__IO_PAGE_FAULT_UDIS86_HPP__)
#define __IO_PAGE_FAULT_UDIS86_HPP__

//
// local includes
//
#include "core/machine/arch/x86/emulation/in_out.hpp"
#include "udis86-1.4/udis86.h"

//
// handle x86 in & out instructions
//
template <enum ud_mnemonic_code mnemonic>
inline int x86_handle_in_out(x86_machine &machine, x86_context &ctx, const ud_t &ud)
{
    static_assert((mnemonic == UD_Iin) || (mnemonic == UD_Iout), "invalid mnemonic");

    //
    // determine I/O port
    //
    const ud_operand &port_op=ud.operand[(mnemonic == UD_Iin) ? 1 : 0];
    l4_port_t port=0;

    switch (port_op.type) {
        // always byte immediate
        case UD_OP_IMM: port=port_op.lval.ubyte; break;
        // or always register DX
        case UD_OP_REG: port=ctx.edx() & 0xffff; break;

        default:
            log::error("bad operand for instruction at "l4_gva_fmt", expected DX or immediate\n", ctx.ip());
            return -L4_ENOTFOUND;
    }

    //
    // with opsize prefix it is a 16-bit access, so call handler
    //
    if (ud.pfx_opr)
        return (mnemonic == UD_Iin) ? x86_in<uint16_t>(machine, ctx, port) : x86_out<uint16_t>(machine, ctx, port);

    //
    // otherwise determine access size and call handler
    //
    const ud_operand &size_op=ud.operand[(mnemonic == UD_Iin) ? 0 : 1];

    if (L4VMM_DEBUG_X86)
        // always register operand: AL, AX or EAX
        if (size_op.type != UD_OP_REG) {
            log::error("bad operand for instruction at "l4_gva_fmt", expected AL, AX or EAX\n", ctx.ip());
            return -L4_EINVAL;
        }

    switch (size_op.base) {
        case UD_R_AL:
            return (mnemonic == UD_Iin) ? x86_in<uint8_t>(machine, ctx, port) : x86_out<uint8_t>(machine, ctx, port);
        case UD_R_AX:
            return (mnemonic == UD_Iin) ? x86_in<uint16_t>(machine, ctx, port) : x86_out<uint16_t>(machine, ctx, port);
        case UD_R_EAX:
            return (mnemonic == UD_Iin) ? x86_in<uint32_t>(machine, ctx, port) : x86_out<uint32_t>(machine, ctx, port);

        default:
            log::error("bad operand for instruction at "l4_gva_fmt", expected AL, AX or EAX\n", ctx.ip());
            return -L4_ENOTFOUND;
    }
}

//
// handle all x86 I/O space instructions
//
inline int x86_machine::handle_io_page_fault(x86_context &ctx)
{
    logd(L4VMM_DEBUG_X86 >= 2, L4VMM_DEBUG": emulating I/O space instruction at "l4_gva_fmt"\n", ctx.ip());

    // replaces ud_init(&ud)
    ud_t ud;
    memset(&ud, 0, sizeof(ud));
    ud_set_mode(&ud, 32);
    ud_set_input_buffer(&ud, reinterpret_cast<uint8_t *>(ctx.ip()), 32);

    // decode instruction
    const uint8_t ins_size=ud_disassemble(&ud);
    if (unlikely(ud.mnemonic == UD_Idb)) {
        log::error("error decoding instruction at "l4_gva_fmt"\n", ctx.ip());
        return -L4_EINVAL;
    }

    // get REP prefix
    const bool rep=ud.pfx_rep || ud.pfx_repe || ud.pfx_repne;

    //
    // call handler functions
    //
    int err=0;
    switch (ud.mnemonic) {
        case UD_Iin:    err=x86_handle_in_out<UD_Iin>(*this, ctx, ud);  break;
        case UD_Iout:   err=x86_handle_in_out<UD_Iout>(*this, ctx, ud); break;

        case UD_Iinsb:  err=x86_ins<uint8_t>(*this, ctx, rep);          break;
        case UD_Iinsw:  err=x86_ins<uint16_t>(*this, ctx, rep);         break;
        case UD_Iinsd:  err=x86_ins<uint32_t>(*this, ctx, rep);         break;
        case UD_Ioutsb: err=x86_outs<uint8_t>(*this, ctx, rep);         break;
        case UD_Ioutsw: err=x86_outs<uint16_t>(*this, ctx, rep);        break;
        case UD_Ioutsd: err=x86_outs<uint32_t>(*this, ctx, rep);        break;

        default:
            log::error("bad instruction at "l4_gva_fmt" [%d]\n"
                             "  expected in/out or ins/outs\n", ctx.ip(), ins_size);
            return -L4_ENOTSUPP;
    }

    if (err) return err;
    // skip instruction
    ctx.ip()+=ins_size;
    return 0;
}

#endif

// ***** end of source ***** //