piix_ide_config_space.hpp

#if !defined(__PIIX3_IDE_CONFIG_SPACE_HPP__)
#define __PIIX3_IDE_CONFIG_SPACE_HPP__

//
// local includes
//
#include "devices/common.hpp"

struct __packed(piix_ide_config_space) : public pci_config_header64
{
    //
    // IDE Timing Modes (read-write) at offset: 0x40
    //     primary channel:   0x40-0x41 == ATA0 == IDE_timing_modes[0]
    //     secondary channel: 0x42-0x43 == ATA1 == IDE_timing_modes[1]
    //
    union IDE_timing_modes
    {
        le_uint16_t raw;

        struct __packed()
        {
          #if LITTLE_ENDIAN_BITFIELD
            //
            // drive 0 aka. the channel's master
            //
            unsigned enable_fast_timing_bank0       : 1;    // bit 0
            unsigned enable_IORDY_sample_point0     : 1;    // bit 1
            unsigned enable_prefetch_and_posting0   : 1;    // bit 2
            unsigned enable_DMA_timing0             : 1;    // bit 3

            //
            // drive 1 aka. the channel's slave
            //
            unsigned enable_fast_timing_bank1       : 1;    // bit 4
            unsigned enable_IORDY_sample_point1     : 1;    // bit 5
            unsigned enable_prefetch_and_posting1   : 1;    // bit 6
            unsigned enable_DMA_timing1             : 1;    // bit 7

            //
            // recovery_time & IORDY_sample_point for the channel's master
            //
            unsigned recovery_time                  : 2;    // bit 8-9
            unsigned reserved10_11                  : 2;    // bit 10-11
            unsigned IORDY_sample_point             : 2;    // bit 12-13
            unsigned enable_slave_timings           : 1;    // bit 14
            unsigned enable_IDE_decode              : 1;    // bit 15
          #elif BIG_ENDIAN_BITFIELD
            unsigned enable_DMA_timing1             : 1;    // bit 7
            unsigned enable_prefetch_and_posting1   : 1;    // bit 6
            unsigned enable_IORDY_sample_point1     : 1;    // bit 5
            unsigned enable_fast_timing_bank1       : 1;    // bit 4 (0 = 16-bit, 1 = 32-bit)
            unsigned enable_DMA_timing0             : 1;    // bit 3
            unsigned enable_prefetch_and_posting0   : 1;    // bit 2
            unsigned enable_IORDY_sample_point0     : 1;    // bit 1
            unsigned enable_fast_timing_bank0       : 1;    // bit 0 (0 = 16-bit, 1 = 32-bit)

            unsigned enable_IDE_decode              : 1;    // bit 15
            unsigned enable_slave_timings           : 1;    // bit 14
            unsigned IORDY_sample_point             : 2;    // bit 12-13
            unsigned reserved10_11                  : 2;    // bit 10-11
            unsigned recovery_time                  : 2;    // bit 8-9
          #else
            #error unknown bitfield order. fix this.
          #endif
        };

        ACCESS_FUNCTORS(IDE_timing_modes&, uint16_t, raw)
        NUMERIC_ACCESS_OPERATORS(IDE_timing_modes&, uint16_t, raw)
        NUMERIC_ACCESS_OPERATORS(IDE_timing_modes&, le_uint16_t, raw)
        INCREMENT_OPERATORS(IDE_timing_modes, raw)
    } IDE_timing_modes[2];

    //
    // slave IDE Timing Modes (read-write) at offset: 0x44
    //     this register is only effective, if enable_slave_timings is set.
    //     used for both channels. the bits controlling the master are
    //     in the IDE Timing Modes register.
    //
    union slave_IDE_timing_modes
    {
        uint8_t raw;

        struct __packed()
        {
          #if LITTLE_ENDIAN_BITFIELD
            //
            // channel 0 aka. primary
            //
            unsigned ata0_recovery_time             : 2;    // bit 0-1
            unsigned ata0_IORDY_sample_point        : 2;    // bit 2-3

            //
            // channel 1 aka. secondary
            //
            unsigned ata1_recovery_time             : 2;    // bit 4-5
            unsigned ata1_IORDY_sample_point        : 2;    // bit 6-7
          #elif BIG_ENDIAN_BITFIELD
            unsigned ata1_IORDY_sample_point        : 2;    // bit 6-7
            unsigned ata1_recovery_time             : 2;    // bit 4-5
            unsigned ata0_IORDY_sample_point        : 2;    // bit 2-3
            unsigned ata0_recovery_time             : 2;    // bit 0-1
          #else
            #error unknown bitfield order. fix this.
          #endif
        };

        ACCESS_FUNCTORS(slave_IDE_timing_modes&, uint8_t, raw)
        NUMERIC_ACCESS_OPERATORS(slave_IDE_timing_modes&, uint8_t, raw)
        INCREMENT_OPERATORS(slave_IDE_timing_modes, raw)
    } slave_IDE_timing_modes;

    //
    // unused
    //
    uint8_t unused45_47[0x47-0x44];

    //
    // Synchronous DMA Control Register (read-write) at offset: 0x48
    //
    union sdma_control
    {
        uint8_t raw;

        struct __packed()
        {
          #if LITTLE_ENDIAN_BITFIELD
            unsigned ata00_sdma_enable              : 1;    // bit 0
            unsigned ata01_sdma_enable              : 1;    // bit 1
            unsigned ata10_sdma_enable              : 1;    // bit 2
            unsigned ata11_sdma_enable              : 1;    // bit 3
            unsigned reserved4_7                    : 4;    // bit 4-7
          #elif BIG_ENDIAN_BITFIELD
            unsigned reserved4_7                    : 4;    // bit 4-7
            unsigned ata11_sdma_enable              : 1;    // bit 3
            unsigned ata10_sdma_enable              : 1;    // bit 2
            unsigned ata01_sdma_enable              : 1;    // bit 1
            unsigned ata00_sdma_enable              : 1;    // bit 0
          #else
            #error unknown bitfield order. fix this.
          #endif
        };

        ACCESS_FUNCTORS(sdma_control&, uint8_t, raw)
        NUMERIC_ACCESS_OPERATORS(sdma_control&, uint8_t, raw)
        INCREMENT_OPERATORS(sdma_control, raw)
    } sdma_control;

    //
    // unused
    //
    uint8_t unused49;

    //
    // Synchronous DMA Timing Register (read-write) at offset: 0x4a
    //
    union sdma_timing
    {
        le_uint16_t raw;

        struct __packed()
        {
          #if LITTLE_ENDIAN_BITFIELD
            unsigned ata00_cycle_time               : 2;    // bit 0-1
            unsigned reserved2_3                    : 2;    // bit 2-3
            unsigned ata01_cycle_time               : 2;    // bit 4-5
            unsigned reserved6_7                    : 2;    // bit 6-7

            unsigned ata10_cycle_time               : 2;    // bit 8-9
            unsigned reserved10_11                  : 2;    // bit 10-11
            unsigned ata11_cycle_time               : 2;    // bit 12-13
            unsigned reserved14_15                  : 2;    // bit 14-15
          #elif BIG_ENDIAN_BITFIELD
            unsigned reserved6_7                    : 2;    // bit 6-7
            unsigned ata01_cycle_time               : 2;    // bit 4-5
            unsigned reserved2_3                    : 2;    // bit 2-3
            unsigned ata00_cycle_time               : 2;    // bit 0-1

            unsigned reserved14_15                  : 2;    // bit 14-15
            unsigned ata11_cycle_time               : 2;    // bit 12-13
            unsigned reserved10_11                  : 2;    // bit 10-11
            unsigned ata10_cycle_time               : 2;    // bit 8-9
          #else
            #error unknown bitfield order. fix this.
          #endif
        };

        ACCESS_FUNCTORS(sdma_timing&, uint16_t, raw)
        NUMERIC_ACCESS_OPERATORS(sdma_timing&, uint16_t, raw)
        NUMERIC_ACCESS_OPERATORS(sdma_timing&, le_uint16_t, raw)
        INCREMENT_OPERATORS(sdma_timing, raw)
    } sdma_timing;

    //
    // unused
    //
    uint8_t unused4c_53[0x53-0x4b];

    //
    // IDE I/O Configuration Register (read-write) at offset: 0x54
    //
    union ide_config
    {
        le_uint32_t raw;

        struct __packed()
        {
          #if LITTLE_ENDIAN_BITFIELD
            //
            // 0 = 33 MHz base clock for Ultra ATA timings.
            // 1 = 66 MHz base clock for Ultra ATA timings.
            //
            unsigned ata00_base_clock               : 1;    // bit 0
            unsigned ata01_base_clock               : 1;    // bit 1
            unsigned ata10_base_clock               : 1;    // bit 2
            unsigned ata11_base_clock               : 1;    // bit 3

            //
            // 0 = 40 conductor cable is present.
            // 1 = 80 conductor cable is present.
            //
            unsigned ata00_channel_cable_reporting  : 1;    // bit 4
            unsigned ata01_channel_cable_reporting  : 1;    // bit 5
            unsigned ata10_channel_cable_reporting  : 1;    // bit 6
            unsigned ata11_channel_cable_reporting  : 1;    // bit 7

            unsigned reserved8_9                    : 2;    // bit 8-9
            unsigned write_pingpong_enable          : 1;    // bit 10
            unsigned reserved11                     : 1;    // bit 11
            unsigned fast_ata00_base_clock          : 1;    // bit 12
            unsigned fast_ata01_base_clock          : 1;    // bit 13
            unsigned fast_ata10_base_clock          : 1;    // bit 14
            unsigned fast_ata11_base_clock          : 1;    // bit 15

            unsigned primary_sig_mode               : 2;    // bit 16-17
            unsigned secondary_sig_mode             : 2;    // bit 18-19
            unsigned miscellaneous_scratchpad       : 4;    // bit 20-23
          #elif BIG_ENDIAN_BITFIELD
            unsigned ata11_channel_cable_reporting  : 1;    // bit 7
            unsigned ata10_channel_cable_reporting  : 1;    // bit 6
            unsigned ata01_channel_cable_reporting  : 1;    // bit 5
            unsigned ata00_channel_cable_reporting  : 1;    // bit 4
            unsigned ata11_base_clock               : 1;    // bit 3
            unsigned ata10_base_clock               : 1;    // bit 2
            unsigned ata01_base_clock               : 1;    // bit 1
            unsigned ata00_base_clock               : 1;    // bit 0

            unsigned fast_ata11_base_clock          : 1;    // bit 15
            unsigned fast_ata10_base_clock          : 1;    // bit 14
            unsigned fast_ata01_base_clock          : 1;    // bit 13
            unsigned fast_ata00_base_clock          : 1;    // bit 12
            unsigned reserved11                     : 1;    // bit 11
            unsigned write_pingpong_enable          : 1;    // bit 10
            unsigned reserved8_9                    : 2;    // bit 8-9

            unsigned miscellaneous_scratchpad       : 4;    // bit 20-23
            unsigned secondary_sig_mode             : 2;    // bit 18-19
            unsigned primary_sig_mode               : 2;    // bit 16-17
          #else
            #error unknown bitfield order. fix this.
          #endif

            unsigned reserved24_31                  : 8;    // bit 24-31
        };

        ACCESS_FUNCTORS(ide_config&, uint32_t, raw)
        NUMERIC_ACCESS_OPERATORS(ide_config&, uint32_t, raw)
        NUMERIC_ACCESS_OPERATORS(ide_config&, le_uint32_t, raw)
        INCREMENT_OPERATORS(ide_config, raw)
    } ide_config;

    //
    // unused
    //
    uint8_t unused58_bf[0xbf-0x57];

    //
    // Trapping Control Register (read-write) at offset: 0xc0
    //
    union trap_control
    {
        uint8_t raw;

        struct __packed()
        {
          #if LITTLE_ENDIAN_BITFIELD
            unsigned ata00                          : 1;    // bit 0
            unsigned ata01                          : 1;    // bit 1
            unsigned reserved2_7                    : 6;    // bit 2-7
          #elif BIG_ENDIAN_BITFIELD
            unsigned reserved2_7                    : 6;    // bit 2-7
            unsigned ata01                          : 1;    // bit 1
            unsigned ata00                          : 1;    // bit 0
          #else
            #error unknown bitfield order. fix this.
          #endif
        };

        ACCESS_FUNCTORS(trap_control&, uint8_t, raw)
        NUMERIC_ACCESS_OPERATORS(trap_control&, uint8_t, raw)
        INCREMENT_OPERATORS(trap_control, raw)
    } trap_control;

    //
    // unused
    //
    uint8_t unusedc1_c3[0xc3-0xc0];

    //
    // Trapping Status Register (read-write-clear) at offset: 0xc4
    //
    union trap_status
    {
        uint8_t raw;

        struct __packed()
        {
          #if LITTLE_ENDIAN_BITFIELD
            unsigned ata00                          : 1;    // bit 0
            unsigned ata01                          : 1;    // bit 1
            unsigned reserved2_7                    : 6;    // bit 2-7
          #elif BIG_ENDIAN_BITFIELD
            unsigned reserved2_7                    : 6;    // bit 2-7
            unsigned ata01                          : 1;    // bit 1
            unsigned ata00                          : 1;    // bit 0
          #else
            #error unknown bitfield order. fix this.
          #endif
        };

        ACCESS_FUNCTORS(trap_status&, uint8_t, raw)
        NUMERIC_ACCESS_OPERATORS(trap_status&, uint8_t, raw)
        INCREMENT_OPERATORS(trap_status, raw)
    } trap_status;

    //
    // reserved
    //
    uint8_t unusedc5_ff[0xff-0xc4];

    //
    // constructor
    //
    piix_ide_config_space(void)
    {
        memset(this, 0, static_unsigned_min<sizeof(piix_ide_config_space), 256>::value);
    }
};

static_assert(sizeof(piix_ide_config_space) == 256, "piix_ide_config_space's size must be 256");

#endif

// ***** end of source ***** //