IPC/Capabilities Overview

Jonathan S. Shapiro shap at eros-os.org
Thu Jan 1 16:48:48 CET 2004

On Wed, 2003-12-31 at 22:20, M. Edward Borasky wrote:
> > On Wed, 2003-12-31 at 11:39, Rudy Koot wrote:
> > > This goes in against their believe that "A computers get 
> > > faster memory acesss get relativly slower, therefore
> > > memory access should be avoided during IPC". 
> > 
> > Based on history of processor architecture over the last 30 
> > years, this belief is very well motivated. The problem is 
> > likely to get worse, not better.
> Yes, memories get *bigger* but not faster. So memory hierarchies get deeper.
> I wonder if operating systems shouldn't have a "deeper hierarchy" as well
> ... A "nanokernel" that lives in the processor and its registers, a
> "microkernel" that lives in the level 1 cache, etc. 

Actually, this isn't the reason that memory gets slower. The reason is
that clock rate determines levels of logic, and levels of logic
determines L1 cache size.

But there is hope coming. It turns out that we *do* know how to build
main memories that run at current L2 cache speeds or better, and if you
run the weighted memory reference times you'll discover that the best
way to speed up a modern processor is by improving miss performance.

In the end, however, this is only going to give us breathing room.
Fundamentally, there is wire latency on the bus and precharge latencies
in the memory line drivers that need to be there. We can alter the
processes to make these things faster, but we cannot entirely make them
go away.


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