What happens on timeslice overrun?

[Marcus Brinkmann]

At Tue, 22 Nov 2005 20:14:34 +0100,
"Udo A. Steinberg" <us15 at os.inf.tu-dresden.de> wrote:
> 
> On Wed, 21 Sep 2005 18:29:03 +0200 Marcus Brinkmann (MB) wrote:
> 
> MB> I hate to distract from the real issue, but I should note that
> MB> volatile does not do what you describe here.  If you need to make sure
> MB> that you see the write of another thread, you must use a memory
> MB> barrier or another proper synchronization primitive.  "volatile" is
> MB> not the answer.
> 
> I argue that you do NOT need any memory barrier in this case. Cache
> coherency ensures that as soon as CPU1 writes the relevant cache line
> with deadline_miss = 1, it goes invalid on CPU0 and the next read
> from CPU0 for deadline_miss will fetch the cache line from CPU1 and
> both CPUs go to shared.

You are right, I was having a knee-jerk reaction.  Thanks for the correction!

Marcus