PowerPC interrupt setup
kay-uwe.genz at web.de
Sun Feb 26 17:32:18 CET 2006
Hi Joshua, hi @ all,
I start this year with first experiments in implementation of an
kernel (based on L4.X2) on PowerPC, mostly to learn more about
PowerPC/HW and design philosophies. So I read your posting with
attention and have some questions ... and hope your answers would
made it easier for my to understand.
You recommend "enabling virtual addressing immediatly". Did I
understand it right, that you use virtual memory in kernel mode? Is
this only for protection or means this, the kernel memory is vitual?
There are other kernels using virtual memory in kernel mode?
My design doesn't have a kernel section in the tasks address space
(on 32 bit machines a task is 4GB). I agonise to solve some of the
problems with this design. In the case StringItems used to send Msg's
from one space to another (means copy the information in the kernel)
the message buffer on both sides can scattered and located across
page bounderies. Handling this seems easier if the kernel has the
same view to memory and pionters to memory regions (buffers) but this
destroy my approach of lockfreeness, because the String Buffers in
different tasks can by overlap or locate at the same virtual adress.
(The sendphase of StringItems should by interruptable and at any time
it should by possible to handle as much as possible StrinItem sends
in the same time.) Handling this in kernel with the view of real
memory avoid overlapping buffer regions from different threads. Do
you see the issue like I and is there a solution I didn't see?
As I see on the homepage, the kernel runs on a G3 (aka PPC750). So
you use the normal hardware table search?
Thanks for helping.
Am 07.02.2006 um 17:35 schrieb Joshua LeVasseur:
> The PowerPC jumps to predefined code locations when delivering
> interrupts and traps, starting at 0x100 (with virtual addressing
> disabled). You only need to install code at those locations;
> PowerPC has no interrupt descriptors. I recommend enabling virtual
> addressing immediately, even while handling page faults; I've seen
> other kernels implement excessive logic in assembler, executing in
> physical mode; that isn't necessary. I enable virtual addressing
> within 19 or so instructions.
> Maybe try volume 3 here:
> I've never read those documents; I used the 603 architecture manual
> when porting L4Ka::Pistachio.
> Consider reading about how I made my L4Ka::Pistachio PowerPC
> implementation frigging fast:
> It covers:
> - Fast system calls (without wasting a register for a system call
> number, unlike all other kernels out there that I've seen)
> - Fast address space ID management (the way ASIDs were meant to be
> managed on the PowerPC, and again, the other kernels out there are
> doing it wrong)
> - Fast page hash management. Most kernels perform O(n) searches
> through the page hash when manually locating an entry. I instead
> perform O(1) lookups.
> I recommend that you avoid looking at open source kernels for
> guidance. They don't push the limits of PowerPC.
> On Feb 7, 2006, at 16:18, Matthias Lange wrote:
>> I am stuck with porting the Fiasco microkernel to PowerPC. I can't
>> find any clear documentation about how to setup a interrupt
>> description table. So, these are my questions:
>> 1. How is an interrupt descriptor formed on PowerPC? How does it
>> 2. Where (in memory) do I need to store these descriptors?
>> The IBM PowerPC Programming Manual gives me a good overview but no
>> information on how to implement it. Can someone please point me to
>> some meaningful documentation?
More information about the l4-hackers