Instances of lazy scheduling and timeslice donation in L4 implementations

[Gernot Heiser]

Note that the Inside L4 document refers to the old MIPS kernel, which
is one implementation of (and extended) V2 API.

It also, like many other implementations, does time-slice donation
incorrectly (i.e. blindly). Time-slice donation should respect
priorities. I believe that this is fixed in NICTA::Pistachio-embedded,
but the code is the ultimate reference ;-)

Gernot

>>>>> On Fri, 20 Jan 2006 20:21:32 +1100, Sergio Ruocco <sergio.ruocco at nicta.com.au> said:
SR> According to Gernot's "Inside L4/MIPS" Version 2.19 of January 30, 2001
SR> https://www.ertos.nicta.com.au/publications/papers/Heiser:IL4.abstract.pml

SR> Section 2.1.2 (page 7):
SR> Time-slice donation can happen in one of two ways:
SR> � explicitly via the thread switch system call. This call donates the
SR> remainder of the caller�s current time [...]
SR> � implicitly via IPC. IPC operations are often accompanied by a context
SR> switch from the sender to the receiver, in which case the sender�s
SR> current time slice is implicitly donated to the receiver.

SR> and

SR> Section 5.2.3:
SR> " The other point to note is that, while the sender thread is put into
SR> the busy list to allow it to be scheduled again, the context switch to
SR> the receiver is actually performed without any scheduling (lazy
SR> scheduling [Lie93]). The receiver simply continues in the remainder of
SR> the sender�s time slice. This is an instance of time-slice donation in L4."

SR> I assume that the above described cases still hold for most, if not all,
SR> the current L4 implementation(s). The IPC time-slice donation is a
SR> classic optimisation, and ThreadSwitch() is part of the L4 specification.

SR> I have few Qs:


SR> 1) Besides the ones above, are there in the current L4 implementations
SR> other instances of:
SR> 1.1) time-slice donation ?
SR> 1.2) lazy-scheduling ?


SR> 2) If yes, do they affect or are affected in special ways by [kernel]
SR> interrupt threads ?
SR> (I think not, but with implementation/optimisations you never know...)


SR> Thanks

SR> 	Sergio

SR> -- 

SR> --

SR> http://www.cse.unsw.edu.au/~sruocco/
SR> ERTOS Researcher                                              Lecturer
SR> National ICT Australia Ltd.              University of New South Wales

SR> This email and any attachments are confidential. They may contain
SR> legally privileged information or copyright material. You should not
SR> read, copy, use or disclose them without authorisation.  If you are
SR> not an intended recipient, please contact us at once by return email
SR> and then delete both messages.  We do not accept liability in
SR> connection with computer virus, data corruption, delay, interruption,
SR> unauthorised access or unauthorised amendment.  This notice should not
SR> be removed.



SR> _______________________________________________
SR> l4-hackers mailing list
SR> l4-hackers at os.inf.tu-dresden.de
SR> http://os.inf.tu-dresden.de/mailman/listinfo/l4-hackers