fiasco compilation problems

[Udo A. Steinberg]

On Fri, 24 Nov 2006 16:58:33 +0100 Hendrik Tews (HT) wrote:

HT> - the fiasco-ux site says 
HT> 
HT>    Enable at least the following configuration options:
HT> 
HT>        * Target platform (choose UX)
HT>        * Assembler IPC shortcut
HT>        * Generate inline code 
HT> 
HT>   I could neither find IPC shortcut nor inline code.

* Assembler IPC shortcut was hidden by accident because someone thought PF_UX
  is included in PF_PC. The Fiasco maintainer(s) didn't catch that. Following
  patch reverts that silliness.

Index: rules.cml
===================================================================
RCS file: /home/cvs/l4/kernel/fiasco/src/rules.cml,v
retrieving revision 1.171
diff -u -r1.171 rules.cml
--- rules.cml   19 Oct 2006 08:50:54 -0000      1.171
+++ rules.cml   24 Nov 2006 16:19:31 -0000
@@ -462,7 +462,7 @@
 unless IA32 and PF_PC suppress dependent REGPARM3
 unless IA32 suppress dependent PROFILE SYNC_TSC SMALL_SPACES IO_PROT 
                        FINE_GRAINED_CPUTIME  
-unless PF_PC suppress ASSEMBLER_IPC_SHORTCUT
+unless PF_UX or PF_PC suppress ASSEMBLER_IPC_SHORTCUT
 unless IA32 suppress dependent JDB_ACCOUNTING ia32_processor
 unless AMD64 suppress dependent amd64_processor
 require AMD64 implies WATCHDOG==n and GSTABS==n and ABI_X0==n and

* Generate inline code still exists in the "Kernel Debugging" menu.

HT> - Finally fiasco-ux and all the modules were compiled:
HT> 
HT> tandem l4v2 38> ./fiasco
HT> 
HT> 
HT> Fiasco-UX on Linux 2.6.17-2-k7 (i686)
HT> Mapped 64 MB Memory + 0 KB Framebuffer + 0 MB Input Area on FD 3
HT> 
HT> Loading Module 0x00090000-0x00096d44 [sigma0-ux]
HT> Loading Module 0x00120000-0x002bd9f4 [roottask]
HT> 
HT> Bootstrapping...
HT> 
HT> Welcome to Fiasco(ux)!
HT> DD-L4(v2)/x86 microkernel (C) 1998-2006 TU Dresden
HT> Rev: Thu Nov 23 10:27:00 2006 compiled with gcc 4.1.2 for Intel Pentium
HT> 
HT> CPU: AuthenticAMD (F:23:2:0) Model: Athlon 64 X2 (Toledo) at 2418 MHz
HT> 
HT>   32/512 Entry I TLB (4K pages)      8 Entry I TLB (4M pages)
HT>   32/512 Entry D TLB (4K pages)      8 Entry D TLB (4M pages)
HT>   64 KB L1 I Cache (2-way associative, 64 bytes per line)
HT>   64 KB L1 D Cache (2-way associative, 64 bytes per line)
HT> 1024 KB L2 U Cache (8-way associative, 64 bytes per line)
HT> 
HT> Freeing init code/data: 24576 bytes (6 pages)
HT> 
HT> ASSERTION_FAILED (((((*(int *) &(status))) & 0xff) == 0x7f) && ((((*(int *)
HT> &(status))) & 0xff00) >> 8) == 10) in function static unsigned int
HT> Hostproc::create(unsigned int) in
HT> file /home/tews/Fiasco/current/l4/kernel/fiasco/src/kern/ux/hostproc.cpp:120

This sounds like your host kernel uses a VAS split other than 1G/3G. See
http://os.inf.tu-dresden.de/fiasco/ux/status.shtml for details on that.

		- Udo
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