clarification on explicit preemption points in Fiasco IPC
alexander.warg at os.inf.tu-dresden.de
Fri Jun 22 09:20:55 CEST 2007
On Thu, 2007-06-21 at 22:57 +0200, Sergio Ruocco wrote:
> My question is:
> As far as I know, Fiasco is entirely preemptable. Then why sprinkling
> the IPC path with Enable IRQs/NOP NOP/Disable IRQs ?
> Is there a document or a paper that discuss which parts of the kernel
> run with IRQs disabled / enabled ? Preemption disabled / enabled etc. ?
In particular, the Fiasco IPC path for register only IPC runs with
disabled interrupts and has explicit preemption points.
The work of Rene Reusner (unfortunately in German) describes the
trade-off between preemptability and performance of the IPC path.
-------------- next part --------------
A non-text attachment was scrubbed...
Size: 189 bytes
Desc: This is a digitally signed message part
More information about the l4-hackers