clarification on explicit preemption points in Fiasco IPC
sruocco at cse.unsw.edu.au
Fri Jun 22 09:37:21 CEST 2007
Alexander Warg wrote:
> In particular, the Fiasco IPC path for register only IPC runs with
> disabled interrupts and has explicit preemption points.
Then everything else in Fiasco runs with interrupts enabled and it is
preemptable. Is this correct ? Are there notable exceptions ?
> The work of Rene Reusner (unfortunately in German) describes the
> trade-off between preemptability and performance of the IPC path.
Very interesting. It would be good to have an English translation of
this thesis, or a paper based on it.
Thanks a lot for the prompt and informative answer,
Sergio Ruocco, PhD Research Fellow
ruocco at disco.unimib.it / sergio.ruocco at gmail.com NOMADIS Lab.
phone: +39-02-6448-7879 mobile, embedded real-time systems
skype: 'sergioruocco' Università degli Studi di Milano-Bicocca, Italy
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