clarification on explicit preemption points in Fiasco IPC
adam at os.inf.tu-dresden.de
Tue Jun 26 13:59:46 CEST 2007
On Fri Jun 22, 2007 at 09:37:21 +0200, Sergio Ruocco wrote:
> Alexander Warg wrote:
> >In particular, the Fiasco IPC path for register only IPC runs with
> >disabled interrupts and has explicit preemption points.
> Then everything else in Fiasco runs with interrupts enabled and it is
> preemptable. Is this correct ? Are there notable exceptions ?
Adam adam at os.inf.tu-dresden.de
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