16-bit code and L4

[Valery V. Sedletski]

>On Thu Jun 21, 2007 at 03:55:24 +1300, Valery V. Sedletski wrote:
>> >>> 2) Must all the segment registers be CS == DS == ES == FS == GS == SS == FLAT in L4 usermode 
>> >programs (in Intel 
>> >>> architecture implementation)? Or, there exist a possibility to use segments other than FLAT?
>> >>>   
>> >>Fiasco preserves some of these segments (e.g., GS to support thread 
>> >>local storage). However, unless OS/2 makes use of these segments in 
>> >>32-bit mode there is no need to change these from a flat setting.
>> >
>> >It seems, that OS/2 does not use GS (GS seems to be always == 0), at least, in application programs.
>> >
>> 
>> But also FS is used to address a structure named Thread Info Block
>> (TIB), it is also not flat (it has a limit=0x30) So, FS is used by
>> OS/2 and programs depend on it. GS seems to be not used, and ES and DS
>> are generally flat.
>
>Fiasco makes some GDT slots available to userland so that FS and GS can
>be used with those.
>

And how to access these GDT descriptors from userland? Is this documented somewhere? Can usermode task change attributes of these 
descriptors (such as "16-bits" attribute)? Are they (descriptors) somehow mapped to requestor's address space or how else can usermode 
task 
modify these descriptors? Or, can usermode task only load selectors corresponding to these descriptors, but not modify descriptors itself? So 
it 
is with Fiasco, and what about Pistachio? (Is this mailing list the right place to ask such questions, or it is better to ask them at 
l4ka at ira.uka.de?)

And what about DS/ES? Can usermode task load these registers with another selector, as with FS/GS?

>
>
>Adam
>-- 
>Adam                 adam at os.inf.tu-dresden.de
>  Lackorzynski         http://os.inf.tu-dresden.de/~adam/
>