clarification on explicit preemption points in Fiasco IPC

[Alexander Warg]

On Thu, 2007-06-21 at 22:57 +0200, Sergio Ruocco wrote:
> My question is:
> 
> As far as I know, Fiasco is entirely preemptable. Then why sprinkling
> the IPC path with Enable IRQs/NOP NOP/Disable IRQs ?
> 
> Is there a document or a paper that discuss which parts of the kernel
> run with IRQs disabled / enabled ? Preemption disabled / enabled etc. ?

In particular, the Fiasco IPC path for register only IPC runs with
disabled interrupts and has explicit preemption points.
The work of Rene Reusner (unfortunately in German) describes the
trade-off between preemptability and performance of the IPC path.

http://os.inf.tu-dresden.de/papers_ps/reusner-diplom.pdf

-- 
Alex
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