memory problems on Fiasco porting
adam at os.inf.tu-dresden.de
Thu Feb 12 22:32:13 CET 2009
On Wed Feb 11, 2009 at 21:44:55 +0800, Tsai, Tung-Chieh wrote:
> I'm working on porting Fiasco to an ARM(922T) platform.
> Currently, I can get into kernel debugger, and successfully
> leave the `Calibrating timer loop'. But then I stuck in
> Thread::init_workload, fail to create sigma0_thread. ARM
> processor would raise a data abort exception and then
> goto 0xffff0010.
> It seems failed because trying to load an illegal virtual
> address at 0xc0080004, which doing this at :
This is the first access to the TCB of the sigma0 thread and actually
what should happen in init_workload. The TCBs are pulled in on request.
> I guess the problem maybe becuase some architecture
> porting part still has problem, or because the sigma0_task
> create for sigma0_thread setting wrong memory space,
> because I've some memory space setting incorrect.
The the data abort happens it should end up in the page fault handler
and further on make a page visible at 0xc0080000. Does this happen or
> Honestly, I don't know where setting the virtual address
> translation for 0xd0000000 ~ 0xc0000000(_tcbs_1 to
> phys_offset), is this range use for each thread's tcb ?
Yes, actually TCBs go from 0xc0000000 - 0xe0000000 usually.
> And where can I get more information about Fiasco's
> memory layout? for example, what does Mem_layout::Tcbs
> and Mem_layout::User_max means? which range of memory
> is used for specific purpose, for example, I/O device(seems
> is 0xef100000 ~ ) ?
There's the mem_layout-arm.cpp file which describes the generic layout.
The platform specific layout is described in kern/arm/bsp/foo/mem_layout...
User_max is the address there user virtual memory end and Tcbs is the
address there the TCBs start.
Adam adam at os.inf.tu-dresden.de
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