Fiasco.OC IPC performance

Gernot Heiser gernot at cse.unsw.edu.au
Sat Feb 5 00:43:11 CET 2011


What are the actual figures, and on what processor? Practical limits on IPC round-trip times (i.e. ping-pong) depend on the architecture. 

On x86 it is in the range of 500-5000 cycles depending on the microarchitecture (worst on Pentium-4, better on more recent implementations, and historically better on AMD than on Intel processors, although that might have changed since I last looked at it in detail). Pistachio IPC performance used to be fairly optimal, but probably hasn't been maintained, so may not show the full benefit of the more recent microarchitectures. But if you're seeing more than 2000 cycles round-trip on a recent x86 processor you're a fair bit away from optimal.

For comparison, on ARM we're seeing about 300-500 cycles depending on architecture version and core implementation.

Gernot

On 04/02/2011, at 10:47 , Chen Tian wrote:

> Hello,
> 
> I am trying to compare the IPC performance between Pistachio and
> Fiasco.OC. I found the performances are almost the same for the
> Pingpong benchmark (I modified the one in Pistachio so that it can run
> with Fiasco.OC as well). I notice that if I turn off "tracebuffer" and
> "perfmon counter" switches when compiling Pistachio kernel, the IPC of
> Pistachio is much faster -- about 150x speedup for Pingpong! I tried
> to do the same thing for Fiasco.OC by turning off debugging related
> switches. However, I was not able to observe any performance
> improvement. I wonder if what config options that can dramatically
> affect the IPC performance for Fiasco.OC.
> 
> Also, I will appreciate it if anyone could explain to me the major IPC
> implementation differences.
> 
> Thanks,
> 
> Chen
> 
> _______________________________________________
> l4-hackers mailing list
> l4-hackers at os.inf.tu-dresden.de
> http://os.inf.tu-dresden.de/mailman/listinfo/l4-hackers





More information about the l4-hackers mailing list