Fiasco.OC IPC performance

Gernot Heiser gernot at cse.unsw.edu.au
Sat Feb 5 02:46:08 CET 2011


[Apologies for top-quote in previous mail.]

On 05/02/2011, at 12:01 , Chen Tian wrote:

> The architecture is x86. For pistachio, I got ~2000 cycles for a
> round-trip IPC with all kernel debug features disabled.  

That makes sense. May not be optimal, but not too far out.

> With kernel debug (i.e. tracebuffer etc.) features, the number is about 300K
> cycles.

Makes sense too.

> For Fiasco.OC, the number is also around 300K cycles no matter jdb
> debugging switch is on or off.

Clearly way too high. Can't comment on Fiasco, though.

Gernot



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