[L4 on realview Cortex A9] Failing on board check during fiasco bootup

Adam Lackorzynski adam at os.inf.tu-dresden.de
Fri Feb 18 11:51:34 CET 2011

On Fri Feb 18, 2011 at 11:31:49 +0530, Naveen Chandrakar wrote:
> We were able to overcome the qemu: fatal: Unimplemented cp15 register write
> (c9, c14, {0, 0})
> by modifying helper.c in qemu code (cleaned c9 data reg) and L4 booting went
> ahead till it starts Sigma0.

Those are performance counters which can be disabled altogether. There
isn't just an option for that currently because it was always available
so far.
> But as you pointed out earlier (for smp running) that cp15-c7
> implementation/data structure(qemu:Cpu.h) is missing (which doesn't looks
> like it'll be implimented anytime sooner in qemu).

No, it has been implemented. Patch reviews are currently going on on the
qemu list. It will probably still take a bit until it hits git.

> The patch/workaround which you've mentioned, i'm supposing is a L4 patch for
> overcoming qemu's shortcoming.
> Where can i access this patch/hack (as part of next release or in SVN) ?

I'm not trying to add workarounds to Fiasco but to add the missing bits to
qemu. The next svn refresh will probably contain those little bits for
not requiring perfcounters.

Adam                 adam at os.inf.tu-dresden.de
  Lackorzynski         http://os.inf.tu-dresden.de/~adam/

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