L4 on ARM: cache coherency and virtual address space

Michal Schulz michal at genesi-usa.com
Sun May 8 22:18:28 CEST 2011


Hello,

I am implementing an USB stack for ARM machine maintained by the L4
microkernel. It works quite well at the moment - USB hubs and HID
devices are working properly.  However, there are few open issues
there:

1. Since ARM machine I use does not provide cache snooping, i.e. I
have to flush/invalidate the caches manually, I've attempted to use
the l4_cache_dma_coherent function. It did worked to some degree, but
it flushed/invalidated only *some* lines of cache within requested
region, instead of *all* lines of cache. Since I've failed to trace
the bug, I've extended sigma0 with new functionality - ability to map
uncached memory. I still don't like my hack though and I would like to
find an official way to either change the attributes (from cached to
uncached) of given page, or have fully working l4_cache_dma_coherent.

2. The USB stack is a multithreaded app where I would like to have
different servers (e.g. server for HID input events, server for mass
storage devices). Unfortunately a server seemed to work only when
started from the main thread. Why is it so? Was that my fault?

3. When the mass storage server receives either read or write call, it
needs to map caller's memory in uncached manner. Moreover, USB stack
needs *physical* address of the caller's buffer. How can I find that
out?

with best regards,
Michal.

-- 
Michal Schulz




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