Get lost in Fiasco.OC regarding the io-apic IRQ number and CPU interrupt numbers

Christian Ehrhardt ehrhardt at
Tue Jul 31 14:11:02 CEST 2012


On Mon, Jul 30, 2012 at 05:42:25PM -0700, Chen Tian wrote:
> As confirmed by Udo, I thought the vector of an IO-APIC pin is the one used
> to index idt, which is from 0x20-0x37. But I just checked the idt using
> kernel debugger and found that many entries between 0x20 and 0x37 are
> marked as reserved. Several defined ones can be found in entry.S. However,
> I noticed that 48 entries from 0x50 to 0x7f are actually defined. Are those
> for the 48 pins in my two IO-APICs?  Why have the vectors changed? And
> where can I found the corresponding CPU interrupt handlers?

IDT vector allocation is as follows:
- 0..0x1f: CPU Exceptions. Vectors cannot be modified by user space.
- 0x20..0x2f: PIC/IO-APIC IRQs 0..0xf.
- 0x30..0x3f: L4 System calls or reserved.
- 0x40..Irq_pin_msi::Vector_offs(0x50)-1: PIC/IO-APIC IRQs 0x10..0x1f
- Irq_pin_msi::Vector_offs(0x50)..APIC_IRQ_BASE(0x90)-0x11:
  Usable for MSI/MSI-X IRQs starting at zero or for PIC/IO-APIC
  irqs starting at 0x20.
  Reserved for APIC internal use (APIC timer, IPIs etc.).

If you have two IO-APICs, i.e. 0x30 GSIs and you want to use MSI/MSIX,
you need to change APIC_IRQ_BASE and Irq_pin_msi::Vector_offs to avoid
IDT slot conflicts.

> Another thing that confuses me is that th function  "irq_interrupt" in file
> "dirq-ia32-ux.cpp". Where does it get called? I found one call site in
> entry.S, which seems to use an interrupt number (int - 0x20) as the first
> parameter. But why this number is used as a pointer that pointing to an irq
> object?

The normal path to irq_interrupt is via the code generated in
Entry_code::setup(). The path generated by the INTERRUPT define
in entry.S appears to be a buggy, AFAICS.

     regards   Christian

More information about the l4-hackers mailing list