Fiasco.OC interrupt handling
d.waddington at samsung.com
Mon Jan 28 18:55:38 CET 2013
I'm looking into the interrupt handling in Fiasco.OC r.40 (x86/amd64).
Browsing the code, it appears that the IDT only gets set up on CPU 0 and
therefore on a multicore platform all interrupt handling from the
kernel's perspective is from core 0. Of course the user-level handlers
themselves may be elsewhere. Do I have this correct or am I
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