1 maximal supported CPUs

Irvanda Kurniadi irvanda.k at gmail.com
Wed Apr 16 03:39:39 CEST 2014


On Wed, Apr 16, 2014 at 6:30 AM, Adam Lackorzynski <
adam at os.inf.tu-dresden.de> wrote:

> On Tue Apr 15, 2014 at 17:48:55 +0900, Irvanda Kurniadi wrote:
> > I was trying to run ex_thread_migrate in my system. I use 8 active
> > processor. I did config the fiasco to support the multi processor to 8
> > Maximal supported number of CPUs. Then I ran the thread_migrate example
> > program. After I ran the program, there was only 1 maximal supported
> CPUs.
> > I even tried to add the -smp 8 while using qemu. But, there wasn't any
> > difference. Please let me know how to fix this.
>
> Is there any message such as 'CPU[1]: goes to idle loop' while booting?
>
>
No, only CPU[0] appeared. Here is the message shown in the console by the
way.

L4 Bootstrapper
  Build: #1 Tue Apr 15 17:06:38 KST 2014, x86-32, 4.6.1
  RAM: 0000000000000000 - 000000000009f3ff: 637kB
  RAM: 0000000000100000 - 0000000017ffcfff: 392180kB
  Total RAM: 383MB
  Moving up to 7 modules behind 1100000
  moving module 00 { 2e6000-354fbf } -> { 1877000-18e5fbf } [454592]
  moving module 01 { 355000-3a9adc } -> { 18e6000-193aadc } [346845]
  moving module 02 { 3aa000-5dd0fe } -> { 193b000-1b6e0fe } [2306303]
  moving module 03 { 5de000-6fe4ca } -> { 1100000-12204ca } [1180875]
  moving module 04 { 6ff000-93375f } -> { 1221000-145575f } [2312032]
  moving module 05 { 934000-9340b3 } -> { 1456000-14560b3 } [180]
  moving module 06 { 935000-a5c15b } -> { 1457000-157e15b } [1208668]
  Scanning /home/ganis/etri2/l4re-mpich/obj/fiasco/ia32/fiasco -serial_esc
  Scanning /home/ganis/etri2/l4re-mpich/obj/l4/x86/bin/x86_586/l4f/sigma0
  Scanning /home/ganis/etri2/l4re-mpich/obj/l4/x86/bin/x86_586/l4f/moe
rom/thread_migrate.cfg
  Bootloader MMAP:
    [        0,     9f400) RAM (1)
    [    9f400,     a0000) reserved (2)
    [    f0000,    100000) reserved (2)
    [   100000,  17ffd000) RAM (1)
    [ 17ffd000,  18000000) reserved (2)
    [ feffc000,  ff000000) reserved (2)
  Relocated mbi to [0x2e0000-0x2e02a7]
  Loading /home/ganis/etri2/l4re-mpich/obj/fiasco/ia32/fiasco
  Loading ganis/etri2/l4re-mpich/obj/l4/x86/bin/x86_586/l4f/sigma0
  Loading me/ganis/etri2/l4re-mpich/obj/l4/x86/bin/x86_586/l4f/moe
  find kernel info page...
  found kernel info page at 0x400000
Regions of list 'regions'
    [        0,       fff] {     1000} Arch   BIOS
    [    9f400,     9ffff] {      c00} Arch   BIOS
    [    f0000,     fffff] {    10000} Arch   BIOS
    [   100000,    10b197] {     b198} Sigma0
ganis/etri2/l4re-mpich/obj/l4/x86/bin/x86_586/l4f/sigma0
    [   140000,    18e25f] {    4e260} Root
me/ganis/etri2/l4re-mpich/obj/l4/x86/bin/x86_586/l4f/moe
    [   2d0000,    2e4427] {    14428} Boot   bootstrap
    [   2e0000,    2e03a4] {      3a5} Root   Multiboot info
    [   300000,    38ffff] {    90000} Kern
/home/ganis/etri2/l4re-mpich/obj/fiasco/ia32/fiasco
    [   400000,    474fff] {    75000} Kern
/home/ganis/etri2/l4re-mpich/obj/fiasco/ia32/fiasco
    [  1100000,   157e15b] {   47e15c} Root   Module
    [ 17ffd000,  17ffffff] {     3000} Arch   BIOS
    [ feffc000,  feffffff] {     4000} Arch   BIOS
  API Version: (87) experimental
  Sigma0 config    ip:001001dc sp:002df150
  Roottask config  ip:001401c4 sp:00000000
  Starting kernel /home/ganis/etri2/l4re-mpich/obj/fiasco/ia32/fiasco at
003007b8

Welcome to Fiasco.OC (ia32)!
L4/Fiasco.OC ia32 microkernel (C) 1998-2013 TU Dresden
Rev: rexporte compiled with gcc 4.6.1 for Intel Pentium    []
Build: #1 Tue Apr 15 17:05:00 KST 2014

Performance-critical config option(s) detected:
  CONFIG_NDEBUG is off
  CONFIG_NO_FRAME_PTR is off

Superpages: yes
Kmem:: cpu page at 17ff9000 (4096Bytes)
ACPI-Init
ACPI: RSDP[0xfda20]    r00 OEM:BOCHS.
ACPI: RSDT[0x203fd270]    r01 OEM:BOCHS. OEMTID:BXPCRSDT
ACPI: FACP[0x203ffd30]    r01 OEM:BOCHS. OEMTID:BXPCFACP
ACPI: SSDT[0x203fd410]    r01 OEM:BOCHS. OEMTID:BXPCSSDT
ACPI: APIC[0x203fd2f0]    r01 OEM:BOCHS. OEMTID:BXPCAPIC
ACPI: HPET[0x203fd2b0]    r01 OEM:BOCHS. OEMTID:BXPCHPET
IO-APIC: MADT = 0x203fd2f0
IO-APIC[ 0]: struct: 0x203fd35c adr=fec00000
IO-APIC[ 0]: pins 24
  PIN[ 0m]: vector=20, del=0, dm=physical, dest=0 (high, edge)
  PIN[ 1m]: vector=21, del=0, dm=physical, dest=0 (high, edge)
  PIN[ 2m]: vector=22, del=0, dm=physical, dest=0 (high, edge)
  PIN[ 3m]: vector=23, del=0, dm=physical, dest=0 (high, edge)
  PIN[ 4m]: vector=24, del=0, dm=physical, dest=0 (high, edge)
  PIN[ 5m]: vector=25, del=0, dm=physical, dest=0 (high, edge)
  PIN[ 6m]: vector=26, del=0, dm=physical, dest=0 (high, edge)
  PIN[ 7m]: vector=27, del=0, dm=physical, dest=0 (high, edge)
  PIN[ 8m]: vector=28, del=0, dm=physical, dest=0 (high, edge)
  PIN[ 9m]: vector=29, del=0, dm=physical, dest=0 (high, edge)
  PIN[10m]: vector=2a, del=0, dm=physical, dest=0 (high, edge)
  PIN[11m]: vector=2b, del=0, dm=physical, dest=0 (high, edge)
  PIN[12m]: vector=2c, del=0, dm=physical, dest=0 (high, edge)
  PIN[13m]: vector=2d, del=0, dm=physical, dest=0 (high, edge)
  PIN[14m]: vector=2e, del=0, dm=physical, dest=0 (high, edge)
  PIN[15m]: vector=2f, del=0, dm=physical, dest=0 (high, edge)
  PIN[16m]: vector=30, del=0, dm=physical, dest=0 (high, edge)
  PIN[17m]: vector=31, del=0, dm=physical, dest=0 (high, edge)
  PIN[18m]: vector=32, del=0, dm=physical, dest=0 (high, edge)
  PIN[19m]: vector=33, del=0, dm=physical, dest=0 (high, edge)
  PIN[20m]: vector=34, del=0, dm=physical, dest=0 (high, edge)
  PIN[21m]: vector=35, del=0, dm=physical, dest=0 (high, edge)
  PIN[22m]: vector=36, del=0, dm=physical, dest=0 (high, edge)
  PIN[23m]: vector=37, del=0, dm=physical, dest=0 (high, edge)
IO-APIC: dual 8259: yes
IO-APIC: ovr[ 0] 00 -> 2
IO-APIC: ovr[ 1] 05 -> 5
IO-APIC: ovr[ 2] 09 -> 9
IO-APIC: ovr[ 3] 0a -> a
IO-APIC: ovr[ 4] 0b -> b
Allocate cpu_mem @ 0xfe3fb400
FPU0: SSE
Local APIC[00]: version=14 max_lvt=5
APIC ESR value before/after enabling: 00000000/00000000
Using the Local APIC timer on vector 90 (Periodic Mode) for scheduling
SERIAL ESC: allocated IRQ 4 for serial uart
SERIAL ESC: allocated IRQ 4 for serial uart
Not using serial hack in slow timer handler.
Enable MSI support: chained IRQ mgr @ 0xfe3fb150
Absolute KIP Syscalls using: Sysenter
CPU[0]: GenuineIntel (6:3:3:0)[00000633] Model: QEMU Virtual CPU version
0.14.1 at 2133MHz

  32 KB L1 I Cache (8-way associative, 64 bytes per line)
  32 KB L1 D Cache (8-way associative, 64 bytes per line)
2048 KB L2 U Cache (8-way associative, 64 bytes per line)

Freeing init code/data: 28672 bytes (7 pages)

Calibrating timer loop... done.
MDB: use page size: 22
MDB: use page size: 12
SIGMA0: Hello!
  KIP @ 400000
  Found Fiasco: KIP syscalls: yes
  allocated 4KB for maintenance structures
SIGMA0: Dump of all resource maps
RAM:------------------------
[0:1000;9efff]
[0:10c000;13ffff]
[4:140000;18efff]
[0:18f000;2dffff]
[4:2e0000;2e0fff]
[0:2e1000;3fffff]
[0:46e000;10fffff]
[4:1100000;157efff]
[0:157f000;1614bfff]
IOMEM:----------------------
[0:0;fff]
[0:9f000;fffff]
[0:17ffd000;febfffff]
[0:fec01000;fedfffff]
[0:fee01000;ffffffff]
IO PORTS--------------------------
[0:0;fffffff]
MOE: Hello world
MOE: found 355972 KByte free memory
MOE: found RAM from 1000 to 1614c000
MOE: allocated 353 KByte for the page array @0x1000
MOE: virtual user address space [0-bfffffff]
MOE: rom name space cap -> [C:501000]
  BOOTFS: [1100000-12204cb] [C:503000] l4re
  BOOTFS: [1221000-1455760] [C:504000] ned
  BOOTFS: [1456000-14560b4] [C:505000] thread_migrate.cfg
  BOOTFS: [1457000-157e15c] [C:506000] ex_thread_migrate
MOE: cmdline: /home/ganis/etri2/l4re-mpich/obj/l4/x86/bin/x86_586/l4f/moe
rom/thread_migrate.cfg
MOE: Starting: rom/ned rom/thread_migrate.cfg
MOE: loading 'rom/ned'
Ned says: Hi World!
Ned: loading file: 'rom/thread_migrate.cfg'
migrate | 1 maximal supported CPUs.
migrate | Only found 1 CPU.

Regards,

Irvanda
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