Testing Fiasco.OC+L4re on ODROID-X2(Exynos4412)

Reinier Millo Sánchez rmillo at uclv.cu
Tue May 5 07:28:46 CEST 2015


Hi Adam
>> >    FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard,
>> >    p: dbl/sngl
>> >
>> >    KERNEL: Warning: No page-fault handler for 0xee202214, error
>> >    0x94000848, pc f0039420
>> >
>> >Somebody have tested Fiasco.OC+L4re on ODROID-X2 or another Exynos 4412
>> >platform?
> On this platform this seems to be some pattern. However, last time I
> tried it worked for me. So, hmm, could you try another compiler version
> and see if it changes behavior? Maybe this gives us some hints.
I'm using a linaro toolchain 
(gcc-linaro-arm-linux-gnueabihf-4.8-2014.03_x86_64). I have tried the 
arm-none-eabi toolchain in Debian repository but fails compiling the 
snapshot.
I have made some progress trying to run FiascoOC+L4re on Odroid-X2. 
There are some changes that I have made:
I have modified the file "l4/mk/platforms/exynos4.conf" adapting 
Exynos4's platform to Odroid-X2. In this case the RAM size differs 
(Odroid-X2 have 2Gb). In this file I have configured the UART for serial 
output (I'm using UART 1).

    PLATFORM_RAM_BASE       = 0x40000000
    -  PLATFORM_RAM_SIZE_MB  = 1024
    + PLATFORM_RAM_SIZE_MB  = 2047
    + PLATFORM_UART_NR          = 1

Booting the generated image I have detected that bootstrap's server is 
not using UART 1 for output. I have modified the "init" function on 
"l4/pkg/bootstrap/server/src/platform/exynos.cc"  to use the configured 
UART on the platform file modified above.

    unsigned long uart_base;
    -  unsigned uart_nr = 2;
    + unsigned uart_nr = PLATFORM_UART_NR;

I have tried to compile and test the image on the Odroid-X2, but fails 
the execution, this is the serial output:

    L4 Bootstrapper
       Build: #18 Sat May  2 15:56:00 CDT 2015, 4.8.3 20140303 (prerelease)
       Scanning up to 2047 MB RAM, starting at offset 32MB
       Memory size is 2047MB (40000000 - bfefffff)
       Limiting 'RAM' region   [ 40000000,  bfefffff] { 7ff00000} to [
    40000000,  bcffffff] { 7d000000} due to 3024 MB address limit
       RAM: 0000000040000000 - 00000000bcffffff: 2048000kB
       Total RAM: 2000MB
       Scanning fiasco
       Scanning sigma0
       Scanning moe
       Moving up to 5 modules behind 41100000
       moving module 02 { 410b4000-410e565f } -> { 411a5000-411d665f }
    [202336]
       moving module 01 { 410aa000-410b3377 } -> { 4119b000-411a4377 }
    [37752]
       moving module 00 { 41043000-410a9daf } -> { 41134000-4119adaf }
    [421296]
       moving module 04 { 41029000-410425b3 } -> { 4111a000-411335b3 }
    [103860]
       moving module 03 { 4100f000-41028493 } -> { 41100000-41119493 }
    [103572]
       Loading fiasco
       Loading sigma0
       Loading moe
       find kernel info page...
       found kernel info page at 0x40002000
    Regions of list 'regions'
         [ 40000000,  400000e3] {       e4} Root   mbi_rt
         [ 40001000,  40001aff] {      b00} Kern   fiasco
         [ 40002000,  40076fff] {    75000} Kern   fiasco
         [ 40090000,  4009681b] {     681c} Sigma0 sigma0
         [ 40098000,  4009e177] {     6178} Sigma0 sigma0
         [ 40140000,  4018b4ab] {    4b4ac} Root   moe
         [ 41000000,  4100e4ff] {     e500} Boot   bootstrap
         [ 41100000,  41133fff] {    34000} Root   Module
       API Version: (87) experimental
       Sigma0 config    ip:40090100 sp:00000000
       Roottask config  ip:4014020c sp:00000000
       Starting kernel fiasco at 400012c8
    Hello from Startup::stage2
    Per_cpu_data_alloc: (orig: 0xf0063a50-0xf00644d0)
    Number of IRQs available at this GIC: 160
    FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard,
    p: dbl/sngl

    KERNEL: Warning: No page-fault handler for 0xee202214, error
    0x94000848, pc f0039420

I have been testing and changing the compiling configuration. Using the 
below configuration to compile Fiasco.OC, the system boots and hangs at 
"Calibrating timer loop...":

    Platform Timer -> Multi-core timer
    Use ExtGic -> True
    Execution Model -> TrustZone normal side
    Secure Monitor Interface -> Mobicore
    Enable multi processor support -> True
    Maximal supported number of CPUs -> 4

This is the serial output when tested the image on Odroid-X2:

    L4 Bootstrapper

    Build: #56 Tue May 5 01:08:40 CDT 2015, 4.8.3 20140303 (prerelease)

    Scanning up to 2047 MB RAM, starting at offset 32MB

    Memory size is 2047MB (40000000 - bfefffff)

    Limiting 'RAM' region [ 40000000, bfefffff] { 7ff00000} to [
    40000000, bcffffff] { 7d000000} due to 3024 MB address limit

    RAM: 0000000040000000 - 00000000bcffffff: 2048000kB

    Total RAM: 2000MB

    Scanning fiasco

    Scanning sigma0

    Scanning moe

    Moving up to 5 modules behind 41100000

    moving module 02 { 41090000-410c165f } -> { 41181000-411b265f } [202336]

    moving module 01 { 41086000-4108f377 } -> { 41177000-41180377 } [37752]

    moving module 00 { 41043000-4108534f } -> { 41134000-4117634f } [271184]

    moving module 04 { 41029000-410425b3 } -> { 4111a000-411335b3 } [103860]

    moving module 03 { 4100f000-41028493 } -> { 41100000-41119493 } [103572]

    Loading fiasco

    Loading sigma0

    Loading moe

    find kernel info page...

    found kernel info page at 0x40002000

    Regions of list 'regions'

    [ 40000000, 400000e3] { e4} Root mbi_rt

    [ 40001000, 40001aff] { b00} Kern fiasco

    [ 40002000, 4004efff] { 4d000} Kern fiasco

    [ 40090000, 4009681b] { 681c} Sigma0 sigma0

    [ 40098000, 4009e177] { 6178} Sigma0 sigma0

    [ 40140000, 4018b4ab] { 4b4ac} Root moe

    [ 41000000, 4100e4ff] { e500} Boot bootstrap

    [ 41100000, 41133fff] { 34000} Root Module

    API Version: (87) experimental

    Sigma0 config ip:40090100 sp:00000000

    Roottask config ip:4014020c sp:00000000

    Starting kernel fiasco at 400012c8

    Hello from Startup::stage2

    Per_cpu_data_alloc: (orig: 0xf0040110-0xf0040b18)

    Number of IRQs available at this GIC: 160

    FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard,
    p: dbl/sngl

    Watchdog initialized

    SERIAL ESC: allocated IRQ 85 for serial uart

    Not using serial hack in slow timer handler.


    Welcome to Fiasco.OC (arm)!

    L4/Fiasco.OC arm microkernel (C) 1998-2013 TU Dresden

    Rev: unknown compiled with gcc 4.8.3 for Samsung Exynos []

    Build: #68 Tue May 5 01:08:28 CDT 2015

    Per_cpu_data_alloc: (orig: 0xf0040110-0xf0040b18)


    KERNEL: Warning: Buddy::alloc: Size mismatch: a08 v 1000

    Allocate 2568 bytes (3KB) for CPU[4] local storage (offset=13a4ef0,
    0xf13e5000-0xf13e5a08)

    Timer for CPU0 is at IRQ 28

    Number of CPUs: 4

    Calibrating timer loop... Per_cpu_data_alloc: (orig:
    0xf0040110-0xf0040b18)


    KERNEL: Warning: Buddy::alloc: Size mismatch: a08 v 1000

    Allocate 2568 bytes (3KB) for CPU[1] local storage (offset=13a6ef0,
    0xf13e7000-0xf13e7a08)

    FPU1: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard,
    p: dbl/sngl

    Per_cpu_data_alloc: (orig: 0xf0040110-0xf0040b18)

    Timer for CPU1 is at IRQ 28


    KERNEL: Warning: Buddy::alloc: Size mismatch: a08 v 1000

    CPU[1]: goes to idle loop

    Allocate 2568 bytes (3KB) for CPU[2] local storage (offset=13a9ef0,
    0xf13ea000-0xf13eaa08)

    FPU2: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard,
    p: dbl/sngl

    Per_cpu_data_alloc: (orig: 0xf0040110-0xf0040b18)

    Timer for CPU2 is at IRQ 28


    KERNEL: Warning: Buddy::alloc: Size mismatch: a08 v 1000

    CPU[2]: goes to idle loop

    Allocate 2568 bytes (3KB) for CPU[3] local storage (offset=13acef0,
    0xf13ed000-0xf13eda08)

    FPU3: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard,
    p: dbl/sngl

    Timer for CPU3 is at IRQ 28

    CPU[3]: goes to idle loop

I think that the problem now is with the Exynos4's Timers, but i have 
been reviewing the implementations and it seems fine.
Is there anything wrong on my configuration or somebody have any idea?

Best regards

-- 
Lic. Reinier Millo Sánchez
Centro de Estudios de Informática
Universidad Central "Marta Abreu" de Las Villas
Carretera a Camajuaní Km 5 1/2
Santa Clara, Villa Clara, Cuba
CP 54830

"antes de discutir ... respira;
   antes de hablar ... escucha;
  antes de escribir ... piensa;
   antes de herir ... siente;
  antes de rendirte ... intenta;
   antes de morir ... vive"

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