Question about memory management in L4 Fiasco O.C + L4re

Adam Lackorzynski adam at
Tue Jul 28 23:38:58 CEST 2015


On Tue Jul 28, 2015 at 16:10:04 +0200, Mahdi Aichouch wrote:
> I have a question about the way Fiasco.OC handles IPC.
> If we take a simple example of one thread in address space A that sends an
> array of characters to a second
> thread located in an address space B.
> Since such an array might be large and cannot be transferred using the
> registers.
> How it is transferred to the second thread address space?
> Is it at first allocated on the first thread stack, then copied by Fiasco
> kernel to
> the second thread address space?

We use UTCBs for that. A UTCB is a dedicated memory region that each
thread has. Threads copy their IPC payload into their UTCB and the
kernel then copies the content to the receiver's UTCB.

Adam                 adam at

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