fiasco.oc i.MX7d port
adam at os.inf.tu-dresden.de
Sat Oct 8 00:11:59 CEST 2016
On Wed Oct 05, 2016 at 19:50:45 +0200, Marc CHALAND wrote:
> I'm trying to port fiasco.oc to i.MX7d. It works, but I cannot start second
> core. I set trampoline addr into corresponding GPR and enables CORE1. But
> nothing happens. I saw that trampoline assembler code enables SCU through
> external registers. But with cortex a7, SCU hasn't got external registers.
Yes, must not be done on A7. Disabling this block should be sufficient
regarding the SCU.
> So, I ifdefed it but CPU0 still doesn't startup. Can somebody help me ?
You mean CPU1? Did you also add different setting for SCR? It seems to
be different for imx7.
Adam adam at os.inf.tu-dresden.de
More information about the l4-hackers