MIPS Creator CI20 patches (again)
paul at boddie.org.uk
Tue Feb 6 01:38:25 CET 2018
On Monday 5. February 2018 01.43.55 Paul Boddie wrote:
> No, but the serial output isn't being done reliably in a physical sense, so
> that might be my fault rather than anything the software is doing. Is there
> some kind of assembly language file I should be looking at in the bootstrap
> package, just to see where this all gets started?
Answering my own question here - sorry if this preempts a response! - I can
see the following files of interest:
This should be the first code that runs. Here, I think I probably need to
configure the exception base to let me put exception entry points in a
different location (as mentioned previously). I tested this with my simple
boot payload, and the Ingenic SoC supports it, thankfully.
It also looks like I should only map 16MB pages for the bootstrap memory, not
256MB pages for which the bit pattern employed for the pagemask doesn't look
correct. But since the CI20 boots then perhaps the code somehow does the right
thing (and I haven't checked the JZ4780 manual in case this is documented
there). Finally, I see that the FPU is enabled, but the JZ4740 doesn't have
one, so I omit that code. (I'm using a soft-float compiler made using
Buildroot, by the way.)
This positions various things in the kernel. Here, I want to move the
exception routines to the revised exception base, which appears possible by
setting EXC_BASE. Inspecting the kernel using objdump, I see that the routines
are moved when I do this.
So far, I haven't had any "breakthrough", but I guess it is a matter of
working through the code and identifying any potential pitfalls, such as
loading code into the neighbourhood of 0x80000000 which definitely prevents
booting. Many things can be present to prevent things from working, but it
only takes one of them to still be present to have the same undesirable
Anyway, sorry for the noise!
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