Activating the sigma0 thread in the Fiasco kernel

Adam Lackorzynski adam at
Wed Mar 7 00:27:34 CET 2018

On Tue Mar 06, 2018 at 01:14:25 +0100, Paul Boddie wrote:
> On Tuesday 6. March 2018 00.46.29 Adam Lackorzynski wrote:
> > 
> > All what you write sounds good. In any case the eret must restore state
> > including setting the right interrupt state. Are you getting timer
> > interrupts when sigma0 shall run, or is there silence? Is ESC working to
> > get into jdb?
> Thanks for the reply as usual! :-)
> After Proc::cli is called in user_invoke, I don't think any interrupts will be 
> delivered, and if I display the status register, the IE (interrupt enable) bit 
> is indeed not set. So I wouldn't expect any timer interrupts unless something 
> else enables interrupts again, but I can't find any statement where this gets 
> done.
> Here, I think that I *might* have transcribed some operation incorrectly, 
> leaving interrupts disabled when they should be re-enabled. The eret shouldn't 
> itself re-enable interrupts, as far as I remember from messing around with my 
> own boot payloads, since it merely clears the EXL (exception level) bit which 
> prevents interrupts if set (and then jumps to EPC, of course).
> (Thinking about it, EXL isn't even set when I check the status register, but 
> if allowing interrupts in kernel mode, it is customary to clear it, from what 
> I have read, so maybe Fiasco does that.)
> Now, I have transcribed the di instruction to the supposedly-equivalent status 
> register operations that clear IE, and the ei instruction to the operations 
> that set IE, both of these featuring in the Proc::cli and Proc::sti methods. 
> Maybe these instructions should be transcribed to set and clear EXL, however, 
> even though that is not what di and ei do.
> As for jdb and UART interactions, I've had to use more primitive techniques 
> because I can't establish a reliable physical connection to the relevant pins. 
> Fortunately, I can take over the framebuffer and display simple bit patterns 
> (to keep debugging code at a minimum), and this is how I can comment on things 
> like the status register. Yes, it is a slow and tedious way of working, but 
> I've used it successfully before. :-)
> Do you have any idea where this missing re-enabling statement might be, or 
> should I really be manipulating EXL instead of IE?

The asm code sets cp0_status upon exit which includes enabling
interrupts. Are you sure you're not getting any timer interrupts when
supposedly running inside sigma0? (Flipping some pixels in the timer


More information about the l4-hackers mailing list