Information on implementing L4

Gernot Heiser gernot at
Fri Sep 14 03:48:16 CEST 2018

Hi John,

In terms of what makes L4, the most comprehensive recent document is this: <>


> On 14 Sep 2018, at 10:55, John <john.r.moser at <mailto:john.r.moser at>> wrote:
> Hi all.
> I've been looking at Google and Wikipedia for information about L4, and it's fairly thin.  I've come up with that L4 has read and write registers and performs IPC by fixed-length registers, with all actions synchronous (I guess that means you send a message and block until the target thread reads the message).
> Is there a more concrete document anywhere about implementing an L4 microkernel and what makes it L4?
> I'm surveying the field at the moment and looking at all the advances made in computer software—security, managed language runtimes, hypervisors, real-time OS—and trying to project the possibilities for a next-generation operating system.  There's enough divergence that a rewrite from scratch might make sense; and besides, I've drawn up a method for getting a self-hosting CLR running with only anonymous memory allocation and VFS file page mapping, along with a method of getting the CLR to self-host and getting it up and running before an actual OS kernel.
> In other words:  it's readily-achievable to write a CLR in C#, get it running on itself before the kernel comes up, then load a kernel, VMM, VFS, ABI, scheduler, and so forth—all written in C#, compiled to CIL, and totally independent of the hardware architecture underneath—and then throw away the loader and bring up init.  The kernel would need to use an abstract factory model to do common tasks which require hardware-specific code, and the CLR would need to load an assembly with a concrete factory for the particular hardware and a few built-in native assembly calls; but it's doable.
> This is all theoretical at the moment, and I want to explore the particular edges a little to see what I find out.
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