L4Re - L4 Runtime Environment
vbus_pci
1 // vi:ft=cpp
2 /*
3  * (c) 2014 Sarah Hoffmann <sarah.hoffmann@kernkonzept.com>
4  *
5  * This file is part of TUD:OS and distributed under the terms of the
6  * GNU General Public License 2.
7  * Please see the COPYING-GPL-2 file for details.
8  */
9 
10 #pragma once
11 
12 #include <l4/vbus/vbus>
13 #include <l4/vbus/vbus_pci.h>
14 
15 namespace L4vbus {
16 
17 /**
18  * \brief A Pci host bridge
19  */
20 class Pci_host_bridge : public Device
21 {
22 public:
23  /**
24  * \brief Read from the vPCI configuration space using the PCI root bridge.
25  *
26  * \param bus Bus number
27  * \param devfn Device id (upper 16bit) and function (lower 16bit)
28  * \param reg Register in configuration space to read
29  * \param[out] value Value that has been read
30  * \param width Width to read in bits (e.g. 8, 16, 32)
31  *
32  * \return 0 on success, else failure
33  */
34  int cfg_read(l4_uint32_t bus, l4_uint32_t devfn, l4_uint32_t reg,
35  l4_uint32_t *value, l4_uint32_t width) const
36  {
37  return l4vbus_pci_cfg_read(bus_cap().cap(), _dev, bus,
38  devfn, reg, value, width);
39  }
40 
41 
42  /**
43  * \brief Write to the vPCI configuration space using the PCI root bridge.
44  *
45  * \param bus Bus number
46  * \param devfn Device id (upper 16bit) and function (lower 16bit)
47  * \param reg Register in configuration space to write
48  * \param value Value to write
49  * \param width Width to write in bits (e.g. 8, 16, 32)
50  *
51  * \return 0 on success, else failure
52  */
53  int cfg_write(l4_uint32_t bus, l4_uint32_t devfn, l4_uint32_t reg,
54  l4_uint32_t value, l4_uint32_t width) const
55  {
56  return l4vbus_pci_cfg_write(bus_cap().cap(), _dev, bus,
57  devfn, reg, value, width);
58  }
59 
60 
61  /**
62  * \brief Enable PCI interrupt for a specific device using the PCI root bridge.
63  *
64  * \param bus Bus number
65  * \param devfn Device id (upper 16bit) and function (lower 16bit)
66  * \param pin Interrupt pin (normally as reported in
67  * configuration register INTR)
68  * \param[out] trigger False if interrupt is level-triggered
69  * \param[out] polarity True if interrupt is of low polarity
70  *
71  * \return On success: Interrupt line to be used,
72  * else failure
73  */
74  int irq_enable(l4_uint32_t bus, l4_uint32_t devfn, int pin,
75  unsigned char *trigger, unsigned char *polarity) const
76  {
77  return l4vbus_pci_irq_enable(bus_cap().cap(), _dev, bus,
78  devfn, pin, trigger, polarity);
79  }
80 
81 };
82 
83 
84 /**
85  * \brief A PCI device
86  */
87 class Pci_dev : public Device
88 {
89 public:
90  /**
91  * \brief Read from the device's vPCI configuration space.
92  *
93  * \param reg Register in configuration space to read
94  * \param[out] value Value that has been read
95  * \param width Width to read in bits (e.g. 8, 16, 32)
96  *
97  * \return 0 on success, else failure
98  */
99  int cfg_read(l4_uint32_t reg, l4_uint32_t *value,
100  l4_uint32_t width) const
101  {
102  return l4vbus_pcidev_cfg_read(bus_cap().cap(), _dev, reg, value, width);
103  }
104 
105 
106  /**
107  * \brief Write to the device's vPCI configuration space.
108  *
109  * \param reg Register in configuration space to write
110  * \param value Value to write
111  * \param width Width to write in bits (e.g. 8, 16, 32)
112  *
113  * \return 0 on success, else failure
114  */
115  int cfg_write(l4_uint32_t reg, l4_uint32_t value,
116  l4_uint32_t width) const
117  {
118  return l4vbus_pcidev_cfg_write(bus_cap().cap(), _dev, reg, value, width);
119  }
120 
121 
122  /**
123  * \brief Enable the device's PCI interrupt.
124  *
125  * \param[out] trigger False if interrupt is level-triggered
126  * \param[out] polarity True if interrupt is of low polarity
127  *
128  * \return On success: Interrupt line to be used,
129  * else failure
130  */
131  int irq_enable(unsigned char *trigger, unsigned char *polarity) const
132  {
133  return l4vbus_pcidev_irq_enable(bus_cap().cap(), _dev, trigger, polarity);
134  }
135 
136 };
137 
138 }