# PF: SBSA
# PFDESCR: SystemReady SR (SBSA Level 4)
# PFSELECT: BIT64_CHOICE
# PFSELECT: CAN_ARM_CPU_CORTEX_A76 CAN_ARM_CPU_NEOVERSE_N1
# PFSELECT: ARM_GIC HAVE_ARM_GICV3 HAVE_ARM_GIC_MSI
# PFSELECT: HAS_ARM_PSCI HAS_ARM_PSCI_DYNAMIC ARM_PSCI ARM_ACPI
# PFSELECT: ARM_ASID16
# PFSELECT: HAS_ARM_SVE
# PFSELECT: ARM_IOMMU_COHERENT HAS_IOMMU_ARM_SMMU_V3
# PFDEPENDS: ARM

config ARM_IOMMU_MAX
  int "Maximum number of SMMUs"
  depends on IOMMU
  default 16
  help
    The size of some IOMMU related data structures depend on the number of
    supported IOMMUs. Setting the value too high increases the memory
    allocation overhead. A too low value will prevent the kernel from booting,
    though.

    If in doubt, leave the default (16).

# According to the spec, the SMMU should support stage1 _and_ stage2 tables.
# But on Graviton3 this does not seem to be the case. So use stage2 if we run
# as hypervisor to be on the safe side.
config ARM_IOMMU_STAGE2
	bool
	default y if IOMMU && CPU_VIRT

