17 #ifndef __L4UTIL_PERFORM_H 18 #define __L4UTIL_PERFORM_H 25 extern const char*strp6pmc_event(
l4_uint32_t event);
27 #ifndef CONFIG_PERFORM_ONLY_PROTOTYPES 29 #if ! (defined CPU_PENTIUM ^ defined CPU_P6 ^ defined CPU_K7) 31 #error You must define your target architecture. 32 #error Define EITHER CPU_PENTIUM for Intel Pentium or CPU_P6 for Intel PPro/PII/PIII. 44 static inline void l4_i586_wrmsr(
unsigned reg,
unsigned long long*val){
45 unsigned long dummyeax, dummyecx, dummyedx;
48 ".byte 0xf; .byte 0x30\n" 49 :
"=a" (dummyeax),
"=d" (dummyedx),
"=c" (dummyecx)
50 :
"2" (reg),
"0" (*(
unsigned *)val),
"1" (*((
unsigned *)val+1))
59 static inline void l4_i586_rdmsr(
unsigned reg,
unsigned long long*val){
63 ".byte 0xf; .byte 0x32\n" 64 :
"=a" (*(
unsigned *)val),
"=d" (*((
unsigned *)val+1)),
"=c" (dummy)
81 l4_i586_reset_event_counter(
void){
82 asm volatile(
"xor %%eax, %%eax\n" 88 : : :
"cx",
"ax",
"dx" 93 l4_i586_read_event_counter_long(
long long *counter0,
long long *counter1)
101 "movl %%eax, (%%ebx)\n" 102 "movl %%edx, 4(%%ebx)\n" 103 "movl $0x13, %%ecx\n" 105 "movl %%eax, (%%esi)\n" 106 "movl %%edx, 4(%%esi)\n" 108 :
"b" (counter0),
"S" (counter1)
114 l4_i586_read_event_counter(
int *counter0,
int *counter1)
116 asm volatile(
"pushl %%edx\n" 118 "movl $0x12, %%ecx\n" 120 "movl %%eax, %%ebx\n" 121 "movl $0x13, %%ecx\n" 124 :
"=b" (*counter0),
"=a" (*counter1)
125 :
"1" (0),
"c" (0x11)
130 l4_i586_select_event(
int event0,
int event1)
132 asm volatile(
".byte 0x0f, 0x30\n" 135 "a" (event0 + (event1 << 16)),
141 #define P5_RD_MISS 0x003 142 #define P5_WR_MISS 0x008 143 #define P5_RW_MISS 0x029 144 #define P5_EX_MISS 0x00e 146 #define P5_D_WBACK 0x006 148 #define P5_RW_TLB 0x002 149 #define P5_EX_TLB 0x00d 151 #define P5_A_STALL 0x01f 152 #define P5_W_STALL 0x019 153 #define P5_R_STALL 0x01a 154 #define P5_X_STALL 0x01b 156 #define P5_AGI_STALL 0x01f 158 #define P5_PIPLINE_FLUSH 0x015 160 #define P5_NON_CACHE_RD 0x01e 161 #define P5_NCACHE_REFS 0x01e 162 #define P5_LOCKED_BUS 0x01c 164 #define P5_MEM2PIPE 0x009 165 #define P5_BANK_CONF 0x00a 168 #define P5_INSTRS_EX 0x016 169 #define P5_INSTRS_EX_V 0x017 172 #define P5_CNT_NOTHING (0x00 << 6) 173 #define P5_CNT_EVENT_PL0 (0x01 << 6) 174 #define P5_CNT_EVENT_PL3 (0x02 << 6) 175 #define P5_CNT_EVENT (0x03 << 6) 176 #define P5_CNT_CLOCKS_PL0 (0x05 << 6) 177 #define P5_CNT_CLOCKS_PL3 (0x06 << 6) 178 #define P5_CNT_CLOCKS (0x07 << 6) 233 #define P6_DATA_MEM_REFS 0x43 234 #define P6_DCU_LINES_IN 0x45 235 #define P6_DCU_M_LINES_IN 0x46 236 #define P6_DCU_M_LINES_OUT 0x47 237 #define P6_DCU_MISS_OUTSTANDING 0x48 240 #define P6_IFU_IFETCH 0x80 241 #define P6_IFU_IFETCH_MISS 0x81 242 #define P6_ITLB_MISS 0x85 243 #define P6_IFU_MEM_STALL 0x86 244 #define P6_ILD_STALL 0x87 247 #define P6_L2_IFETCH 0x28 248 #define P6_L2_LD 0x29 249 #define P6_L2_ST 0x2a 250 #define P6_L2_LINES_IN 0x24 251 #define P6_L2_LINES_OUT 0x26 252 #define P6_L2_M_LINES_INM 0x25 253 #define P6_L2_M_LINES_OUTM 0x27 254 #define P6_L2_RQSTS 0x2e 255 #define P6_L2_ADS 0x21 256 #define P6_L2_DBUS_BUSY 0x22 257 #define P6_L2_DBUS_BUSY_RD 0x23 260 #define P6_BUS_DRDY_CLOCKS 0x62 261 #define P6_BUS_LOCK_CLOCKS 0x63 262 #define P6_BUS_REQ_OUTSTANDING 0x60 263 #define P6_BUS_TRAN_BRD 0x65 264 #define P6_BUS_TRAN_RFO 0x66 265 #define P6_BUS_TRAN_WB 0x67 266 #define P6_BUS_TRAN_IFETCH 0x68 267 #define P6_BUS_TRAN_INVAL 0x69 268 #define P6_BUS_TRAN_PWR 0x6a 269 #define P6_BUS_TRANS_P 0x6b 270 #define P6_BUS_TRANS_IO 0x6c 271 #define P6_BUS_TRAN_DEF 0x6d 272 #define P6_BUS_TRAN_BURST 0x6e 273 #define P6_BUS_TRAN_ANY 0x70 274 #define P6_BUS_TRAN_MEM 0x6f 275 #define P6_BUS_DATA_RCV 0x64 276 #define P6_BUS_BNR_DRV 0x61 277 #define P6_BUS_HIT_DRV 0x7a 278 #define P6_BUS_HITM_DRV 0x7b 279 #define P6_BUS_SNOOP_STALL 0x7e 282 #define P6_FLOPS 0xc1 283 #define P6_FP_COMP_OPS 0x10 284 #define P6_FP_ASSIST 0x11 287 #define P6_CYCLES_DIV_BUSY 0x14 290 #define P6_LD_BLOCKS 0x03 291 #define P6_SB_DRAINS 0x04 292 #define P6_MISALING_MEM_REF 0x05 295 #define P6_INST_RETIRED 0xc0 296 #define P6_UOPS_RETIRED 0xc2 297 #define P6_INST_DECODER 0xd0 300 #define P6_HW_INT_RX 0xc8 301 #define P6_CYCLES_INT_MASKED 0xc6 302 #define P6_CYCLES_INT_PENDING_AND_MASKED 0xc7 305 #define P6_BR_INST_RETIRED 0xc4 306 #define P6_BR_MISS_PRED_RETIRED 0xc5 307 #define P6_BR_TAKEN_RETIRED 0xc9 308 #define P6_BR_MISS_PRED_TAKEN_RET 0xca 309 #define P6_BR_INST_DECODED 0xe0 310 #define P6_BTB_MISSES 0xe2 311 #define P6_BR_BOGUS 0xe4 312 #define P6_BACLEARS 0xe6 315 #define P6_RESOURCE_STALLS 0xa2 316 #define P6_PARTIAL_RAT_STALLS 0xd2 319 #define P6_SEGMENT_REG_LOADS 0x06 322 #define P6_CPU_CLK_UNHALTED 0x79 325 #define P6_UNIT_M 0x0800 326 #define P6_UNIT_E 0x0400 327 #define P6_UNIT_S 0x0200 328 #define P6_UNIT_I 0x0100 329 #define P6_UNIT_MESI 0x0f00 331 #define P6_UNIT_SELF 0x0000 332 #define P6_UNIT_ANY 0x2000 343 #define P6CNT_U 0x010000 344 #define P6CNT_K 0x020000 345 #define P6CNT_E 0x040000 346 #define P6CNT_PC 0x080000 347 #define P6CNT_IE 0x100000 348 #define P6CNT_F 0x200000 349 #define P6CNT_EN 0x400000 350 #define P6CNT_IV 0x800000 367 #define MSR_P6_EVNTSEL0 0x186 368 #define MSR_P6_EVNTSEL1 0x187 369 #define MSR_P6_PERFCTR0 0xc1 370 #define MSR_P6_PERFCTR1 0xc2 378 #define l4_i686_rdpmc(cntr, res_p) \ 380 "movl %2, %%ecx # put counter number in \n\ 381 .byte 0xf; .byte 0x33 # RDPMC instruction \n\ 382 movl %%edx, %1 # High order 32 bits \n\ 383 movl %%eax, %0 # Low order 32 bits" \ 384 : "=g" (*(int *)(res_p)), "=g" (*(((int *)res_p)+1)) \ 386 : "ecx", "eax", "edx") 388 static inline l4_uint32_t l4_i686_rdpmc_32(
int cntr){
391 __asm__ __volatile__(
392 ".byte 0xf; .byte 0x33 # RDPMC instruction" 395 :
"ecx",
"eax",
"edx");
399 static inline void l4_i686_select_perfctr_event(
int counter,
400 unsigned long long val){
401 l4_i586_wrmsr(MSR_P6_EVNTSEL0+counter, &val);
404 static inline void l4_i686_select_perfctr0_event(
long long *val){
406 "movl $MSR_P6_EVNTSEL0, %%ecx\n" 407 "movl (%%ebx), %%eax\n" 408 "movl 4(%%ebx), %%edx\n" 414 :
"ax",
"cx",
"dx",
"bx" 422 #define K7CNT_U 0x010000 423 #define K7CNT_K 0x020000 424 #define K7CNT_E 0x040000 425 #define K7CNT_PC 0x080000 426 #define K7CNT_IE 0x100000 427 #define K7CNT_F 0x200000 428 #define K7CNT_EN 0x400000 429 #define K7CNT_IV 0x800000 431 #define MSR_K7_EVNTSEL0 0xC0010000 432 #define MSR_K7_EVNTSEL1 0xC0010001 433 #define MSR_K7_EVNTSEL2 0xC0010002 434 #define MSR_K7_EVNTSEL3 0xC0010003 435 #define MSR_K7_PERFCTR0 0xC0010004 436 #define MSR_K7_PERFCTR1 0xC0010005 437 #define MSR_K7_PERFCTR2 0xC0010006 438 #define MSR_K7_PERFCTR3 0xC0010007 Common L4 ABI Data Types.
#define EXTERN_C_END
End section with C types and functions.
L4 compiler related defines.
#define EXTERN_C_BEGIN
Start section with C types and functions.
unsigned int l4_uint32_t
Unsigned 32bit value.