L4Re - L4 Runtime Environment
vmcs.h
1 /*
2  * Copyright (C) 2017 Kernkonzept GmbH.
3  * Author(s): Philipp Eppelt <philipp.eppelt@kernkonzept.com>
4  *
5  * This file is distributed under the terms of the GNU General Public
6  * License, version 2. Please see the COPYING-GPL-2 file for details.
7  *
8  * As a special exception, you may use this file as part of a free software
9  * library without restriction. Specifically, if other files instantiate
10  * templates or use macros or inline functions from this file, or you compile
11  * this file and link it with other files to produce an executable, this
12  * file does not by itself cause the resulting executable to be covered by
13  * the GNU General Public License. This exception does not however
14  * invalidate any other reasons why the executable file might be covered by
15  * the GNU General Public License.
16  */
17 #pragma once
18 
19 /*
20  * The constants are defined in the Intel Software Developer Manual Volume 3,
21  * Appendix B.
22  */
23 
27 enum L4vcpu_vmx_vmcs_16bit_fields
28 {
29  L4VCPU_VMCS_VPID = 0x0000,
30  L4VCPU_VMCS_PIR_NOTIFICATION_VECTOR = 0x0002,
31  L4VCPU_VMCS_EPTP_INDEX = 0x0004,
32 
33  L4VCPU_VMCS_GUEST_ES_SELECTOR = 0x0800,
34  L4VCPU_VMCS_GUEST_CS_SELECTOR = 0x0802,
35  L4VCPU_VMCS_GUEST_SS_SELECTOR = 0x0804,
36  L4VCPU_VMCS_GUEST_DS_SELECTOR = 0x0806,
37  L4VCPU_VMCS_GUEST_FS_SELECTOR = 0x0808,
38  L4VCPU_VMCS_GUEST_GS_SELECTOR = 0x080a,
39  L4VCPU_VMCS_GUEST_LDTR_SELECTOR = 0x080c,
40  L4VCPU_VMCS_GUEST_TR_SELECTOR = 0x080e,
41  L4VCPU_VMCS_GUEST_INTERRUPT_STATUS = 0x0810,
42 
43  L4VCPU_VMCS_HOST_ES_SELECTOR = 0x0c00,
44  L4VCPU_VMCS_HOST_CS_SELECTOR = 0x0c02,
45  L4VCPU_VMCS_HOST_SS_SELECTOR = 0x0c04,
46  L4VCPU_VMCS_HOST_DS_SELECTOR = 0x0c06,
47  L4VCPU_VMCS_HOST_FS_SELECTOR = 0x0c08,
48  L4VCPU_VMCS_HOST_GS_SELECTOR = 0x0c0a,
49  L4VCPU_VMCS_HOST_TR_SELECTOR = 0x0c0c,
50 };
51 
55 enum L4vcpu_vmx_vmcs_32bit_fields
56 {
57  L4VCPU_VMCS_PIN_BASED_VM_EXEC_CTLS = 0x4000,
58  L4VCPU_VMCS_PRI_PROC_BASED_VM_EXEC_CTLS = 0x4002,
59  L4VCPU_VMCS_EXCEPTION_BITMAP = 0x4004,
60  L4VCPU_VMCS_PAGE_FAULT_ERROR_MASK = 0x4006,
61  L4VCPU_VMCS_PAGE_FAULT_ERROR_MATCH = 0x4008,
62  L4VCPU_VMCS_CR3_TARGET_COUNT = 0x400a,
63 
64  L4VCPU_VMCS_VM_EXIT_CTLS = 0x400c,
65  L4VCPU_VMCS_VM_EXIT_MSR_STORE_COUNT = 0x400e,
66  L4VCPU_VMCS_VM_EXIT_MSR_LOAD_COUNT = 0x4010,
67 
68  L4VCPU_VMCS_VM_ENTRY_CTLS = 0x4012,
69  L4VCPU_VMCS_VM_ENTRY_MSR_LOAD_COUNT = 0x4014,
70  L4VCPU_VMCS_VM_ENTRY_INTERRUPT_INFO = 0x4016,
71  L4VCPU_VMCS_VM_ENTRY_EXCEPTION_ERROR = 0x4018,
72  L4VCPU_VMCS_VM_ENTRY_INSN_LEN = 0x401a,
73 
74  L4VCPU_VMCS_TPR_THRESHOLD = 0x401c,
75  L4VCPU_VMCS_SEC_PROC_BASED_VM_EXEC_CTLS = 0x401e,
76  L4VCPU_VMCS_PLE_GAP = 0x4020,
77  L4VCPU_VMCS_PLE_WINDOW = 0x4022,
78 
79  L4VCPU_VMCS_VM_INSN_ERROR = 0x4400,
80  L4VCPU_VMCS_EXIT_REASON = 0x4402,
81  L4VCPU_VMCS_VM_EXIT_INTERRUPT_INFO = 0x4404,
82  L4VCPU_VMCS_VM_EXIT_INTERRUPT_ERROR = 0x4406,
83  L4VCPU_VMCS_IDT_VECTORING_INFO = 0x4408,
84  L4VCPU_VMCS_IDT_VECTORING_ERROR = 0x440a,
85  L4VCPU_VMCS_VM_EXIT_INSN_LENGTH = 0x440c,
86  L4VCPU_VMCS_VM_EXIT_INSN_INFO = 0x440e,
87 
88  L4VCPU_VMCS_GUEST_ES_LIMIT = 0x4800,
89  L4VCPU_VMCS_GUEST_CS_LIMIT = 0x4802,
90  L4VCPU_VMCS_GUEST_SS_LIMIT = 0x4804,
91  L4VCPU_VMCS_GUEST_DS_LIMIT = 0x4806,
92  L4VCPU_VMCS_GUEST_FS_LIMIT = 0x4808,
93  L4VCPU_VMCS_GUEST_GS_LIMIT = 0x480a,
94  L4VCPU_VMCS_GUEST_LDTR_LIMIT = 0x480c,
95  L4VCPU_VMCS_GUEST_TR_LIMIT = 0x480e,
96  L4VCPU_VMCS_GUEST_GDTR_LIMIT = 0x4810,
97  L4VCPU_VMCS_GUEST_IDTR_LIMIT = 0x4812,
98 
99  L4VCPU_VMCS_GUEST_ES_ACCESS_RIGHTS = 0x4814,
100  L4VCPU_VMCS_GUEST_CS_ACCESS_RIGHTS = 0x4816,
101  L4VCPU_VMCS_GUEST_SS_ACCESS_RIGHTS = 0x4818,
102  L4VCPU_VMCS_GUEST_DS_ACCESS_RIGHTS = 0x481a,
103  L4VCPU_VMCS_GUEST_FS_ACCESS_RIGHTS = 0x481c,
104  L4VCPU_VMCS_GUEST_GS_ACCESS_RIGHTS = 0x481e,
105  L4VCPU_VMCS_GUEST_LDTR_ACCESS_RIGHTS = 0x4820,
106  L4VCPU_VMCS_GUEST_TR_ACCESS_RIGHTS = 0x4822,
107 
108  L4VCPU_VMCS_GUEST_INTERRUPTIBILITY_STATE = 0x4824,
109  L4VCPU_VMCS_GUEST_ACTIVITY_STATE = 0x4826,
110  L4VCPU_VMCS_GUEST_SMBASE = 0x4828,
111  L4VCPU_VMCS_GUEST_IA32_SYSENTER_CS = 0x482a,
112  L4VCPU_VMCS_PREEMPTION_TIMER_VALUE = 0x482e,
113 
114  L4VCPU_VMCS_HOST_IA32_SYSENTER_CS = 0x4c00,
115 };
116 
120 enum L4vcpu_vmx_vmcs_natural_fields
121 {
122  L4VCPU_VMCS_CR0_GUEST_HOST_MASK = 0x6000,
123  L4VCPU_VMCS_CR4_GUEST_HOST_MASK = 0x6002,
124  L4VCPU_VMCS_CR0_READ_SHADOW = 0x6004,
125  L4VCPU_VMCS_CR4_READ_SHADOW = 0x6006,
126  L4VCPU_VMCS_CR3_TARGET_VALUE0 = 0x6008,
127  L4VCPU_VMCS_CR3_TARGET_VALUE1 = 0x600a,
128  L4VCPU_VMCS_CR3_TARGET_VALUE2 = 0x600c,
129  L4VCPU_VMCS_CR3_TARGET_VALUE3 = 0x600e,
130 
131  L4VCPU_VMCS_EXIT_QUALIFICATION = 0x6400,
132  L4VCPU_VMCS_IO_RCX = 0x6402,
133  L4VCPU_VMCS_IO_RSI = 0x6404,
134  L4VCPU_VMCS_IO_RDI = 0x6406,
135  L4VCPU_VMCS_IO_RIP = 0x6408,
136  L4VCPU_VMCS_GUEST_LINEAR_ADDRESS = 0x640a,
137 
138  L4VCPU_VMCS_GUEST_CR0 = 0x6800,
139  L4VCPU_VMCS_GUEST_CR3 = 0x6802,
140  L4VCPU_VMCS_GUEST_CR4 = 0x6804,
141  L4VCPU_VMCS_GUEST_ES_BASE = 0x6806,
142  L4VCPU_VMCS_GUEST_CS_BASE = 0x6808,
143  L4VCPU_VMCS_GUEST_SS_BASE = 0x680a,
144  L4VCPU_VMCS_GUEST_DS_BASE = 0x680c,
145  L4VCPU_VMCS_GUEST_FS_BASE = 0x680e,
146  L4VCPU_VMCS_GUEST_GS_BASE = 0x6810,
147  L4VCPU_VMCS_GUEST_LDTR_BASE = 0x6812,
148  L4VCPU_VMCS_GUEST_TR_BASE = 0x6814,
149  L4VCPU_VMCS_GUEST_GDTR_BASE = 0x6816,
150  L4VCPU_VMCS_GUEST_IDTR_BASE = 0x6818,
151  L4VCPU_VMCS_GUEST_DR7 = 0x681a,
152  L4VCPU_VMCS_GUEST_RSP = 0x681c,
153  L4VCPU_VMCS_GUEST_RIP = 0x681e,
154  L4VCPU_VMCS_GUEST_RFLAGS = 0x6820,
155  L4VCPU_VMCS_GUEST_PENDING_DBG_EXCEPTIONS = 0x6822,
156  L4VCPU_VMCS_GUEST_IA32_SYSENTER_ESP = 0x6824,
157  L4VCPU_VMCS_GUEST_IA32_SYSENTER_EIP = 0x6826,
158 
159  L4VCPU_VMCS_HOST_CR0 = 0x6c00,
160  L4VCPU_VMCS_HOST_CR3 = 0x6c02,
161  L4VCPU_VMCS_HOST_CR4 = 0x6c04,
162  L4VCPU_VMCS_HOST_FS_BASE = 0x6c06,
163  L4VCPU_VMCS_HOST_GS_BASE = 0x6c08,
164  L4VCPU_VMCS_HOST_TR_BASE = 0x6c0a,
165  L4VCPU_VMCS_HOST_GDTR_BASE = 0x6c0c,
166  L4VCPU_VMCS_HOST_IDTR_BASE = 0x6c0e,
167  L4VCPU_VMCS_HOST_IA32_SYSENTER_ESP = 0x6c10,
168  L4VCPU_VMCS_HOST_IA32_SYSENTER_EIP = 0x6c12,
169  L4VCPU_VMCS_HOST_RSP = 0x6c14,
170  L4VCPU_VMCS_HOST_RIP = 0x6c16,
171 };
172 
176 enum L4vcpu_vmx_vmcs_64bit_fields
177 {
178  L4VCPU_VMCS_ADDRESS_IO_BITMAP_A = 0x2000,
179  L4VCPU_VMCS_ADDRESS_IO_BITMAP_B = 0x2002,
180  L4VCPU_VMCS_ADDRESS_MSR_BITMAP = 0x2004,
181  L4VCPU_VMCS_VM_EXIT_MSR_STORE_ADDRESS = 0x2006,
182  L4VCPU_VMCS_VM_EXIT_MSR_LOAD_ADDRESS = 0x2008,
183  L4VCPU_VMCS_VM_ENTRY_MSR_LOAD_ADDRESS = 0x200a,
184  L4VCPU_VMCS_EXECUTIVE_VMCS_POINTER = 0x200c,
185  L4VCPU_VMCS_TSC_OFFSET = 0x2010,
186  L4VCPU_VMCS_VIRTUAL_APIC_ADDRESS = 0x2012,
187  L4VCPU_VMCS_APIC_ACCESS_ADDRESS = 0x2014,
188  L4VCPU_VMCS_PIR_DESCRIPTOR = 0x2016,
189  L4VCPU_VMCS_VM_FUNCTION_CONTROL = 0x2018,
190  L4VCPU_VMCS_EPT_POINTER = 0x201a,
191  L4VCPU_VMCS_EOI_EXIT_BITMAP0 = 0x201c,
192  L4VCPU_VMCS_EOI_EXIT_BITMAP1 = 0x201e,
193  L4VCPU_VMCS_EOI_EXIT_BITMAP2 = 0x2020,
194  L4VCPU_VMCS_EOI_EXIT_BITMAP3 = 0x2022,
195  L4VCPU_VMCS_EPTP_LIST_ADDRESS = 0x2024,
196  L4VCPU_VMCS_VMREAD_BITMAP_ADDRESS = 0x2026,
197  L4VCPU_VMCS_VMWRITE_BITMAP_ADDRESS = 0x2028,
198  L4VCPU_VMCS_VIRT_EXCP_INFO_ADDRESS = 0x202a,
199  L4VCPU_VMCS_XSS_EXITING_BITMAP = 0x202c,
200 
201  L4VCPU_VMCS_GUEST_PHYSICAL_ADDRESS = 0x2400,
202 
203  L4VCPU_VMCS_LINK_POINTER = 0x2800,
204  L4VCPU_VMCS_GUEST_IA32_DEBUGCTL = 0x2802,
205  L4VCPU_VMCS_GUEST_IA32_PAT = 0x2804,
206  L4VCPU_VMCS_GUEST_IA32_EFER = 0x2806,
207  L4VCPU_VMCS_GUEST_IA32_PERF_GLOBAL_CTRL = 0x2808,
208  L4VCPU_VMCS_GUEST_PDPTE0 = 0x280a,
209  L4VCPU_VMCS_GUEST_PDPTE1 = 0x280c,
210  L4VCPU_VMCS_GUEST_PDPTE2 = 0x280e,
211  L4VCPU_VMCS_GUEST_PDPTE3 = 0x2810,
212 
213  L4VCPU_VMCS_HOST_IA32_PAT = 0x2c00,
214  L4VCPU_VMCS_HOST_IA32_EFER = 0x2c02,
215  L4VCPU_VMCS_HOST_IA32_PERF_GLOBAL_CTRL = 0x2c04,
216 };