15 #ifndef __L4UTIL_PERFORM_H 16 #define __L4UTIL_PERFORM_H 23 extern const char*strp6pmc_event(
l4_uint32_t event);
25 #ifndef CONFIG_PERFORM_ONLY_PROTOTYPES 27 #if ! (defined CPU_PENTIUM ^ defined CPU_P6 ^ defined CPU_K7) 29 #error You must define your target architecture. 30 #error Define EITHER CPU_PENTIUM for Intel Pentium or CPU_P6 for Intel PPro/PII/PIII. 42 static inline void l4_i586_wrmsr(
unsigned reg,
unsigned long long*val){
43 unsigned long dummyeax, dummyecx, dummyedx;
46 ".byte 0xf; .byte 0x30\n" 47 :
"=a" (dummyeax),
"=d" (dummyedx),
"=c" (dummyecx)
48 :
"2" (reg),
"0" (*(
unsigned *)val),
"1" (*((
unsigned *)val+1))
57 static inline void l4_i586_rdmsr(
unsigned reg,
unsigned long long*val){
61 ".byte 0xf; .byte 0x32\n" 62 :
"=a" (*(
unsigned *)val),
"=d" (*((
unsigned *)val+1)),
"=c" (dummy)
79 l4_i586_reset_event_counter(
void){
80 asm volatile(
"xor %%rax, %%rax\n" 86 : : :
"cx",
"ax",
"dx" 91 l4_i586_read_event_counter_long(
long long *counter0,
long long *counter1)
99 "mov %%rax, (%%rbx)\n" 100 "mov %%rdx, 4(%%rbx)\n" 103 "mov %%rax, (%%rsi)\n" 104 "mov %%rdx, 4(%%rsi)\n" 106 :
"b" (counter0),
"S" (counter1)
112 l4_i586_read_event_counter(
int *counter0,
int *counter1)
114 asm volatile(
"push %%rdx \n" 115 ".byte 0x0f, 0x30 \n" 116 "mov $0x12, %%rcx \n" 117 ".byte 0x0f, 0x32 \n" 118 "mov %%rax, %%rbx \n" 119 "movl $0x13, %%rcx \n" 122 :
"=b" (*counter0),
"=a" (*counter1)
123 :
"1" (0),
"c" (0x11)
128 l4_i586_select_event(
int event0,
int event1)
130 asm volatile(
".byte 0x0f, 0x30\n" 133 "a" (event0 + (event1 << 16)),
139 #define P5_RD_MISS 0x003 140 #define P5_WR_MISS 0x008 141 #define P5_RW_MISS 0x029 142 #define P5_EX_MISS 0x00e 144 #define P5_D_WBACK 0x006 146 #define P5_RW_TLB 0x002 147 #define P5_EX_TLB 0x00d 149 #define P5_A_STALL 0x01f 150 #define P5_W_STALL 0x019 151 #define P5_R_STALL 0x01a 152 #define P5_X_STALL 0x01b 154 #define P5_AGI_STALL 0x01f 156 #define P5_PIPLINE_FLUSH 0x015 158 #define P5_NON_CACHE_RD 0x01e 159 #define P5_NCACHE_REFS 0x01e 160 #define P5_LOCKED_BUS 0x01c 162 #define P5_MEM2PIPE 0x009 163 #define P5_BANK_CONF 0x00a 166 #define P5_INSTRS_EX 0x016 167 #define P5_INSTRS_EX_V 0x017 170 #define P5_CNT_NOTHING (0x00 << 6) 171 #define P5_CNT_EVENT_PL0 (0x01 << 6) 172 #define P5_CNT_EVENT_PL3 (0x02 << 6) 173 #define P5_CNT_EVENT (0x03 << 6) 174 #define P5_CNT_CLOCKS_PL0 (0x05 << 6) 175 #define P5_CNT_CLOCKS_PL3 (0x06 << 6) 176 #define P5_CNT_CLOCKS (0x07 << 6) 231 #define P6_DATA_MEM_REFS 0x43 232 #define P6_DCU_LINES_IN 0x45 233 #define P6_DCU_M_LINES_IN 0x46 234 #define P6_DCU_M_LINES_OUT 0x47 235 #define P6_DCU_MISS_OUTSTANDING 0x48 238 #define P6_IFU_IFETCH 0x80 239 #define P6_IFU_IFETCH_MISS 0x81 240 #define P6_ITLB_MISS 0x85 241 #define P6_IFU_MEM_STALL 0x86 242 #define P6_ILD_STALL 0x87 245 #define P6_L2_IFETCH 0x28 246 #define P6_L2_LD 0x29 247 #define P6_L2_ST 0x2a 248 #define P6_L2_LINES_IN 0x24 249 #define P6_L2_LINES_OUT 0x26 250 #define P6_L2_M_LINES_INM 0x25 251 #define P6_L2_M_LINES_OUTM 0x27 252 #define P6_L2_RQSTS 0x2e 253 #define P6_L2_ADS 0x21 254 #define P6_L2_DBUS_BUSY 0x22 255 #define P6_L2_DBUS_BUSY_RD 0x23 258 #define P6_BUS_DRDY_CLOCKS 0x62 259 #define P6_BUS_LOCK_CLOCKS 0x63 260 #define P6_BUS_REQ_OUTSTANDING 0x60 261 #define P6_BUS_TRAN_BRD 0x65 262 #define P6_BUS_TRAN_RFO 0x66 263 #define P6_BUS_TRAN_WB 0x67 264 #define P6_BUS_TRAN_IFETCH 0x68 265 #define P6_BUS_TRAN_INVAL 0x69 266 #define P6_BUS_TRAN_PWR 0x6a 267 #define P6_BUS_TRANS_P 0x6b 268 #define P6_BUS_TRANS_IO 0x6c 269 #define P6_BUS_TRAN_DEF 0x6d 270 #define P6_BUS_TRAN_BURST 0x6e 271 #define P6_BUS_TRAN_ANY 0x70 272 #define P6_BUS_TRAN_MEM 0x6f 273 #define P6_BUS_DATA_RCV 0x64 274 #define P6_BUS_BNR_DRV 0x61 275 #define P6_BUS_HIT_DRV 0x7a 276 #define P6_BUS_HITM_DRV 0x7b 277 #define P6_BUS_SNOOP_STALL 0x7e 280 #define P6_FLOPS 0xc1 281 #define P6_FP_COMP_OPS 0x10 282 #define P6_FP_ASSIST 0x11 285 #define P6_CYCLES_DIV_BUSY 0x14 288 #define P6_LD_BLOCKS 0x03 289 #define P6_SB_DRAINS 0x04 290 #define P6_MISALING_MEM_REF 0x05 293 #define P6_INST_RETIRED 0xc0 294 #define P6_UOPS_RETIRED 0xc2 295 #define P6_INST_DECODER 0xd0 298 #define P6_HW_INT_RX 0xc8 299 #define P6_CYCLES_INT_MASKED 0xc6 300 #define P6_CYCLES_INT_PENDING_AND_MASKED 0xc7 303 #define P6_BR_INST_RETIRED 0xc4 304 #define P6_BR_MISS_PRED_RETIRED 0xc5 305 #define P6_BR_TAKEN_RETIRED 0xc9 306 #define P6_BR_MISS_PRED_TAKEN_RET 0xca 307 #define P6_BR_INST_DECODED 0xe0 308 #define P6_BTB_MISSES 0xe2 309 #define P6_BR_BOGUS 0xe4 310 #define P6_BACLEARS 0xe6 313 #define P6_RESOURCE_STALLS 0xa2 314 #define P6_PARTIAL_RAT_STALLS 0xd2 317 #define P6_SEGMENT_REG_LOADS 0x06 320 #define P6_CPU_CLK_UNHALTED 0x79 323 #define P6_UNIT_M 0x0800 324 #define P6_UNIT_E 0x0400 325 #define P6_UNIT_S 0x0200 326 #define P6_UNIT_I 0x0100 327 #define P6_UNIT_MESI 0x0f00 329 #define P6_UNIT_SELF 0x0000 330 #define P6_UNIT_ANY 0x2000 341 #define P6CNT_U 0x010000 342 #define P6CNT_K 0x020000 343 #define P6CNT_E 0x040000 344 #define P6CNT_PC 0x080000 345 #define P6CNT_IE 0x100000 346 #define P6CNT_F 0x200000 347 #define P6CNT_EN 0x400000 348 #define P6CNT_IV 0x800000 365 #define MSR_P6_EVNTSEL0 0x186 366 #define MSR_P6_EVNTSEL1 0x187 367 #define MSR_P6_PERFCTR0 0xc1 368 #define MSR_P6_PERFCTR1 0xc2 376 #define l4_i686_rdpmc(cntr, res_p) \ 378 "mov %2, %%rcx # put counter number in \n\ 379 .byte 0xf; .byte 0x33 # RDPMC instruction \n\ 380 mov %%rdx, %1 # High order 32 bits \n\ 381 mov %%rax, %0 # Low order 32 bits" \ 382 : "=g" (*(int *)(res_p)), "=g" (*(((int *)res_p)+1)) \ 384 : "ecx", "eax", "edx") 386 static inline l4_uint32_t l4_i686_rdpmc_32(
int cntr){
389 __asm__ __volatile__(
390 ".byte 0xf; .byte 0x33 # RDPMC instruction" 393 :
"rcx",
"rax",
"rdx");
397 static inline void l4_i686_select_perfctr_event(
int counter,
398 unsigned long long val){
399 l4_i586_wrmsr(MSR_P6_EVNTSEL0+counter, &val);
402 static inline void l4_i686_select_perfctr0_event(
long long *val){
404 "mov $MSR_P6_EVNTSEL0, %%rcx\n" 405 "mov (%%rbx), %%rax\n" 406 "mov 4(%%rbx), %%rdx\n" 412 :
"ax",
"cx",
"dx",
"bx" 420 #define K7CNT_U 0x010000 421 #define K7CNT_K 0x020000 422 #define K7CNT_E 0x040000 423 #define K7CNT_PC 0x080000 424 #define K7CNT_IE 0x100000 425 #define K7CNT_F 0x200000 426 #define K7CNT_EN 0x400000 427 #define K7CNT_IV 0x800000 429 #define MSR_K7_EVNTSEL0 0xC0010000 430 #define MSR_K7_EVNTSEL1 0xC0010001 431 #define MSR_K7_EVNTSEL2 0xC0010002 432 #define MSR_K7_EVNTSEL3 0xC0010003 433 #define MSR_K7_PERFCTR0 0xC0010004 434 #define MSR_K7_PERFCTR1 0xC0010005 435 #define MSR_K7_PERFCTR2 0xC0010006 436 #define MSR_K7_PERFCTR3 0xC0010007 Common L4 ABI Data Types.
#define EXTERN_C_END
End section with C types and functions.
L4 compiler related defines.
#define EXTERN_C_BEGIN
Start section with C types and functions.
unsigned int l4_uint32_t
Unsigned 32bit value.