L4Re - L4 Runtime Environment
vbus_pci
1 // vi:ft=cpp
2 /*
3  * (c) 2014 Sarah Hoffmann <sarah.hoffmann@kernkonzept.com>
4  *
5  * This file is part of TUD:OS and distributed under the terms of the
6  * GNU General Public License 2.
7  * Please see the COPYING-GPL-2 file for details.
8  */
9 
10 #pragma once
11 
12 #include <l4/vbus/vbus>
13 #include <l4/vbus/vbus_pci.h>
14 
15 namespace L4vbus {
16 
20 class Pci_host_bridge : public Device
21 {
22 public:
35  l4_uint32_t *value, l4_uint32_t width) const
36  {
37  return l4vbus_pci_cfg_read(bus_cap().cap(), _dev, bus,
38  devfn, reg, value, width);
39  }
40 
41 
54  l4_uint32_t value, l4_uint32_t width) const
55  {
56  return l4vbus_pci_cfg_write(bus_cap().cap(), _dev, bus,
57  devfn, reg, value, width);
58  }
59 
60 
74  int irq_enable(l4_uint32_t bus, l4_uint32_t devfn, int pin,
75  unsigned char *trigger, unsigned char *polarity) const
76  {
77  return l4vbus_pci_irq_enable(bus_cap().cap(), _dev, bus,
78  devfn, pin, trigger, polarity);
79  }
80 
81 };
82 
83 
87 class Pci_dev : public Device
88 {
89 public:
99  int cfg_read(l4_uint32_t reg, l4_uint32_t *value,
100  l4_uint32_t width) const
101  {
102  return l4vbus_pcidev_cfg_read(bus_cap().cap(), _dev, reg, value, width);
103  }
104 
105 
116  l4_uint32_t width) const
117  {
118  return l4vbus_pcidev_cfg_write(bus_cap().cap(), _dev, reg, value, width);
119  }
120 
121 
131  int irq_enable(unsigned char *trigger, unsigned char *polarity) const
132  {
133  return l4vbus_pcidev_irq_enable(bus_cap().cap(), _dev, trigger, polarity);
134  }
135 
136 };
137 
138 }
int l4vbus_pcidev_cfg_read(l4_cap_idx_t vbus, l4vbus_device_handle_t handle, l4_uint32_t reg, l4_uint32_t *value, l4_uint32_t width)
Read from the device&#39;s vPCI configuration space.
int l4vbus_pci_cfg_write(l4_cap_idx_t vbus, l4vbus_device_handle_t handle, l4_uint32_t bus, l4_uint32_t devfn, l4_uint32_t reg, l4_uint32_t value, l4_uint32_t width)
Write to the vPCI configuration space using the PCI root bridge.
A PCI device.
Definition: vbus_pci:87
int cfg_write(l4_uint32_t reg, l4_uint32_t value, l4_uint32_t width) const
Write to the device&#39;s vPCI configuration space.
Definition: vbus_pci:115
int irq_enable(unsigned char *trigger, unsigned char *polarity) const
Enable the device&#39;s PCI interrupt.
Definition: vbus_pci:131
int cfg_read(l4_uint32_t reg, l4_uint32_t *value, l4_uint32_t width) const
Read from the device&#39;s vPCI configuration space.
Definition: vbus_pci:99
int irq_enable(l4_uint32_t bus, l4_uint32_t devfn, int pin, unsigned char *trigger, unsigned char *polarity) const
Enable PCI interrupt for a specific device using the PCI root bridge.
Definition: vbus_pci:74
int cfg_write(l4_uint32_t bus, l4_uint32_t devfn, l4_uint32_t reg, l4_uint32_t value, l4_uint32_t width) const
Write to the vPCI configuration space using the PCI root bridge.
Definition: vbus_pci:53
int l4vbus_pci_irq_enable(l4_cap_idx_t vbus, l4vbus_device_handle_t handle, l4_uint32_t bus, l4_uint32_t devfn, int pin, unsigned char *trigger, unsigned char *polarity)
Enable PCI interrupt for a specific device using the PCI root bridge.
int l4vbus_pci_cfg_read(l4_cap_idx_t vbus, l4vbus_device_handle_t handle, l4_uint32_t bus, l4_uint32_t devfn, l4_uint32_t reg, l4_uint32_t *value, l4_uint32_t width)
Read from the vPCI configuration space using the PCI root bridge.
Device on a L4vbus::Vbus.
Definition: vbus:71
int cfg_read(l4_uint32_t bus, l4_uint32_t devfn, l4_uint32_t reg, l4_uint32_t *value, l4_uint32_t width) const
Read from the vPCI configuration space using the PCI root bridge.
Definition: vbus_pci:34
l4vbus_device_handle_t _dev
The device handle for this device.
Definition: vbus:222
A Pci host bridge.
Definition: vbus_pci:20
Definition: vbus:38
L4::Cap< Vbus > bus_cap() const
Access the Vbus capability of the underlying virtual bus.
Definition: vbus:83
int l4vbus_pcidev_irq_enable(l4_cap_idx_t vbus, l4vbus_device_handle_t handle, unsigned char *trigger, unsigned char *polarity)
Enable the device&#39;s PCI interrupt.
int l4vbus_pcidev_cfg_write(l4_cap_idx_t vbus, l4vbus_device_handle_t handle, l4_uint32_t reg, l4_uint32_t value, l4_uint32_t width)
Write to the device&#39;s vPCI configuration space.
unsigned int l4_uint32_t
Unsigned 32bit value.
Definition: l4int.h:40