Hi Adam,
Yes, I have selected "Use ExtGic".
The boot message is the same for both "Standard mode" and " TrustZone normal size"
### Cut start ### Hello from Startup::stage2 Number of IRQs available at this GIC: 160 FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: dbl/sngl Watchdog initialized SERIAL ESC: allocated IRQ 85 for serial uart Not using serial hack in slow timer handler. Welcome to Fiasco.OC (arm)! L4/Fiasco.OC arm microkernel (C) 1998-2013 TU Dresden Rev: r54 compiled with gcc 4.5.2 for Samsung Exynos [] Build: #60 18:37:23 CST 2013
Timer for CPU0 is at IRQ 28 Calibrating timer loop... ### End ###
Here is "TrustZone secure side" ### Cut start ### Hello from Startup::stage2
Number of IRQs available at this GIC: 160
GIC: Switching IRQ 32 to secure
GIC: Switching IRQ 33 to secure
GIC: Switching IRQ 34 to secure
GIC: Switching IRQ 35 to secure
GIC: Switching IRQ 36 to secure
GIC: Switching IRQ 37 to secure
GIC: Switching IRQ 38 to secure
GIC: Switching IRQ 39 to secure
GIC: Switching IRQ 40 to secure GIC: Switching IRQ 41 to secure GIC: Switching IRQ 42 to secure GIC: Switching IRQ 43 to secure GIC: Switching IRQ 44 to secure GIC: Switching IRQ 45 to secure GIC: Switching IRQ 46 to secure GIC: Switching IRQ 47 to secure GIC: Switching IRQ 139 to secure GIC: Switching IRQ 140 to secure GIC: Switching IRQ 80 to secure GIC: Switching IRQ 74 to secure GIC: Switching IRQ 48 to secure GIC: Switching IRQ 49 to secure GIC: Switching IRQ 50 to secure GIC: Switching IRQ 51 to secure GIC: Switching IRQ 52 to secure GIC: Switching IRQ 53 to secure GIC: Switching IRQ 54 to secure GIC: Switching IRQ 55 to secure GIC: Switching IRQ 56 to secure GIC: Switching IRQ 57 to secure GIC: Switching IRQ 58 to secure GIC: Switching IRQ 59 to secure GIC: Switching IRQ 60 to secure GIC: Switching IRQ 61 to secure GIC: Switching IRQ 62 to secure GIC: Switching IRQ 63 to secure GIC: Switching IRQ 64 to secure GIC: Switching IRQ 79 to secure GIC: Switching IRQ 78 to secure ### End ### It stop here.
Any idea?
By the way, the bootstrap issue is fixed now. Thanks!
Chao-Jui
2013/6/6 Adam Lackorzynski adam@os.inf.tu-dresden.de
Hi,
On Wed Jun 05, 2013 at 17:23:30 +0800, Chao-Jui Chang wrote:
After I change the memory to 1023, it runs but stops at ### Timer for CPU0 is at IRQ 28 Calibrating timer loop...
Stopping there typically means that the timer isn't ticking. Looking at your output below, I wondering if you really have selected extgic mode, as the UART irq should be different in that case. On the other side it should not make a difference.
By the way, how to turn on the module loading information during booting?
Probably wrong UART selected in bootstrap. Check l4/pkg/bootstrap/server/src/platform/exynos.cc and set uart_nr to 1.
The latest snapshot and svn only prints message starting from "Hello from Startup::stage2" ### Start cur ### Exynos4412 # run fiasco Partition1: Start Address(0x1000), Size(0x32000) reading bootstrap.raw
803080 bytes read Boot with zImage
Starting kernel ...
Hello from Startup::stage2 Number of IRQs available at this GIC: 160 FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: dbl/sngl Watchdog initialized SERIAL ESC: allocated IRQ 305 for serial uart Not using serial hack in slow timer handler. Welcome to Fiasco.OC (arm)!
Adam
Adam adam@os.inf.tu-dresden.de Lackorzynski http://os.inf.tu-dresden.de/~adam/