I'm trying to port fiasco.oc to i.MX7d. It works, but I cannot start second core. I set trampoline addr into corresponding GPR and enables CORE1. But nothing happens. I saw that trampoline assembler code enables SCU through external registers. But with cortex a7, SCU hasn't got external registers. So, I ifdefed it but CPU0 still doesn't startup. Can somebody help me ?

Regards

Marc