Hi,
On Fri Sep 08, 2006 at 16:07:26 +0900, Á¶¿Ï±Ù wrote:
.........
64 Entry I TLB (4K or 4M pages) 64 Entry D TLB (4K or 4M pages) 12k u-ops T Cache (8-way associative) 8 KB L1 D Cache (4-way associative, 64 bytes per line) 256 KB L2 U Cache (8-way associative, 64 bytes per line)
Freeing init code/data: 16384 bytes(4 pages)
.... Registers' contents showed....
trap 3 (Breakpoint), error 00000000 from kernel mode Panic: terminated due to trap Return reboots, "k" enters L4 kernel debugger...
I don't have a quick answer to what could be going wrong. Please do not omit the register infos, they are valuable! Once we have the instruction pointer we can look further. It's also useful to know your Fiasco kernel configuration. Please append the globalconfig.out file from your kernel build directory to your response. Thanks.
Adam