I'm now feeling a bit silly looking back at the question. Guess what I really want to know is, if I set up MSI interrupts to a specific Local APICs (e.g. core X) should there be any issue in the kernel handling the interrupts on core X?

Daniel

On 01/28/2013 09:55 AM, Daniel Waddington wrote:

Hi,

I'm looking into the interrupt handling in Fiasco.OC r.40 (x86/amd64). Browsing the code, it appears that the IDT only gets set up on CPU 0 and therefore on a multicore platform all interrupt handling from the kernel's perspective is from core 0. Of course the user-level handlers themselves may be elsewhere. Do I have this correct or am I misunderstanding?

Thanks,
Daniel
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