Christian Stueble stueble@amaunet.cs.uni-dortmund.de writes:
That is exactly what io flex pages are designed for. Initially sigma0 has access to all io ports and can use io flex pages to grant port access to other task. If sigma0 grants access a subset of the io address space (adressses which are accessed by in/out instructions) the task gets an io permission bitmap. If sigma0 (or someone else) grants access to the whole io address space l4 changes the iopl so that any thread in this task can access any port and can even disable interrupts.
I understand the x86 manual in that way: i/o access is permitted only if the tasks CPL <= IOPL _and_ if appropriated bits are set to 0.
No, that´s ``or,´´ not ``and.´´
Generally, only two new IPC messages (to the RMGR or sigma0?) are necessary:
Rmgr
- demandPort( port_nr, size )
- releasePort( port_nr, size )
Yes, that´s right.
Does someone know, why the l4 reference manual restricts the granularity of port access to 16 byte?
No, I don´t. Maybe Jochen can shed some light on this?
Michael