Hi,
I'm looking into the interrupt handling in Fiasco.OC r.40
(x86/amd64). Browsing the code, it appears that the IDT only gets
set up on CPU 0 and therefore on a multicore platform all
interrupt handling from the kernel's perspective is from core 0.
Of course the user-level handlers themselves may be elsewhere. Do
I have this correct or am I misunderstanding?
Thanks,
Daniel