Fiasco.OC is a capability based kernel meaning all kernel objects
(including IPC "channels") are addressed via mappable capabilities,
which reside in a task's address space. Pistachio X.2 works with a
global namespace for all kernel objects, which means to avoid existence
leaks you have to globally partition the thread namespace. Both
Fiasco.OC and Pistachio implement UTCBs as the main mechanism for data
exchange between user-level threads and the kernel, which effectively
gives you a 32+ word register IPC. OC supports a quota-like kernel
memory management mechanism, which as far as I know is still missing in
Pistachio X.2. Otherwise, both kernels provide pretty much the same
functionality (HW virtualization included).