Hi Adam, Thank you for your answer.
The Io_register_block_mmio has a shift parameter for spreading out the register offsets, i.e. you should set it two 2. No need to change the register values or clone the driver.
Works like a charm, though doesnt solve my actual problem.
Is there any documented difference between UART0 and UART3?
http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf at page 645 says uart3 is the same as uart0 apart from it having two extra data flow control signals(RTS and CTS). But they should be deactivated since i wrote 0 to the MCR register. Nevertheless I tried out all the different UARTS (0-7) and noticed that i cant access any of the registers on UART4-7 which have only RX and TX like UART0. On UARTS1-3 I can access the registers but get the same wierd error as soon as I try to change the LCR register to access the BRD_LOW and _HIGH registers. Obviously I get an IRQ error if I use UART0 since IRQ 33 is already taken, but i can still read and write to the registers and get the same error as with UART1-3.
I wonder why changing values in the MMIO of UART3 should affect UART0.
This was just my assumption at what could cause the console to crash. In theory ofcourse it shouldnt affect UART0. I just cant think of any other possible cause.
Any Ideas?
Regards, Clemens