hello:
Recently, I consider implementation heritical scheduler on top of the l4 microkernel, But we meet a problem, the Pistachio handled the interrupt in microkernel internal, In that time, I remember a project in TU-Dresden is build on top of microkernel, But it`s implementation in the old l4 interface, just like the Hazelnut that not handled the interrupt (?), The suitation is some microkernel abstract the interrupt and some microkernel not abstract the interrupt. Can we implementation a real time soft mechanism with interrupt abstracted microkernel, the real time ipc, feature as: interrupt generated then a ipc send to handler and switch to the handler at once
Neil
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[Yu Neil]
hello: Recently, I consider implementation heritical scheduler on top of the l4 microkernel, But we meet a problem, the Pistachio handled the interrupt in microkernel internal, In that time, I remember a project in TU-Dresden is build on top of microkernel, But it`s implementation in the old l4 interface, just like the Hazelnut that not handled the interrupt (?), The suitation is some microkernel abstract the interrupt and some microkernel not abstract the interrupt. Can we implementation a real time soft mechanism with interrupt abstracted microkernel, the real time ipc, feature as: interrupt generated then a ipc send to handler and switch to the handler at once
All L4 kernels abstract interrupts as IPC messages to some user-level handler (e.g., a device driver). I don't understand what your problem is.
eSk
[ interrupt abstraction ]
All L4 kernels abstract interrupts as IPC messages to some user-level handler (e.g., a device driver). I don't understand what your problem is.
I guess he wonders wether he has to deal with the interrupt hardware or not (at least, acknowledging the interrupt at the PIC or not). And this differed indeed for the different kernels.
Can we implementation a real time soft mechanism with interrupt abstracted microkernel, the real time ipc, feature as: interrupt generated then a ipc send to handler and switch to the handler at once
I do not get what you mean by "at once". Scheduling dependends on priorities, and if the priority of the interrupt is the highest of the current running threads it is scheduled.
Some time ago, we defined the Omega0 protocol to hide the implementation and architecture-dependent details of interrupt handling. However, currently it is solely implemented for the LV2 API. You should find the paper at out L4 bibliography website: http://os.inf.tu-dresden.de/L4/bib.html#services. The implementation and detailed API description can be found at the remote cvs.
Jork
l4-hackers@os.inf.tu-dresden.de