Maybe we can use the two registers in the Exception IPC as Pagefault IPC
Hello: In the present implementation of exception ipc the two registers are not used but only given with 0. It seems a little bit waste. I mean in the page fault ipc the two registers include address where page fault occurs and instruction pointer which causes the page fault. Can we make exception ipc includes two registers with the next/current eip and esp? It seems not to be bad for this system call because it is a little bit strange that this exception ipc doesn't includes anything useful. Thanks. Cheng Guanghui
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi Cheng,
In the present implementation of exception ipc the two registers are not used but only given with 0. It seems a little bit waste. I mean in the page fault ipc the two registers include address where page fault occurs and instruction pointer which causes the page fault. Can we make exception ipc includes two registers with the next/current eip and esp? It seems not to be bad for this system call because it is a little bit strange that this exception ipc doesn't includes anything useful.
There is no need to put EIP and ESP into registers, because they (as well as other registers) are part of the exception state that can be found in the exception handler's UTCB after receiving an exception message. Cheers, Bjoern -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkrPtV8ACgkQP5ijxgQLUNmi4ACgiCPpnW1uslL1oir1wpY63/iX FBAAoImz8eyyvc3O4PzjANUbDIGBYdt2 =Ey8P -----END PGP SIGNATURE-----
participants (2)
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Björn Döbel -
Guanghui, Cheng