Hi Adam,
Thanks for your quick reply.
After looking tegra2 bsp, I make some memory layout change. Can you help me to check about it [1]?
Another question is about l4re. l4re also need platform init code at pkg/bootstrap/server/src/platform/tegra2.cc I am new to porting. I don't have any idea about how to modify this. Is there any document for reference?
[1] https://www.dropbox.com/s/bjrf5l2d36wa4yw/exynos4.tgz [2] EXYNOS4 datasheet: https://www.dropbox.com/s/fcw5oe5oyjy1yg2/SEC_Exynos4210_pulbic_manual_Ver.0...
Thanks, Chao-Jui
2013/2/13 Adam Lackorzynski adam@os.inf.tu-dresden.de
On Mon Feb 11, 2013 at 12:46:44 +0800, Chao-Jui Chang wrote:
I want to port Fiasco.OC to run on hardkernel's ODROID[1] platform. Could anyone point out the direction of porting Fiasco to me?
I find some BSP info in l4/src/kernel/fiasco/src/kern/arm/bsp, but I
don't
know how to start porting. Which BSP can be the base to modify for EXYNOS platform?
I'd go for tegra2 bsp.
Adam
Adam adam@os.inf.tu-dresden.de Lackorzynski http://os.inf.tu-dresden.de/~adam/
l4-hackers mailing list l4-hackers@os.inf.tu-dresden.de http://os.inf.tu-dresden.de/mailman/listinfo/l4-hackers
On Sat Feb 16, 2013 at 13:17:10 +0800, Chao-Jui Chang wrote:
After looking tegra2 bsp, I make some memory layout change. Can you help me to check about it [1]?
That looks ok except for the 10500000 addresses you need to have another DevicesX_phys_base as those are 1MB chunks. Don't forget to update bootstrap-*.cpp.
Another question is about l4re. l4re also need platform init code at pkg/bootstrap/server/src/platform/tegra2.cc
Yes, at least a UART init is required so that bootstrap output can be seen. Just follow what other BSPs are doing. There not much more to be done.
Adam
l4-hackers@os.inf.tu-dresden.de