Hello everyone, I have some questions regarding object-capabilities and physical memory mapping. - First of all, my goal is to manage and develop drivers on top of Fiasco. The documentation mentions the existence of an I/O server that does not seem to be on the repository anymore. Did I miss any announcement or is the I/O server in development? - As I did not find this server, I tried to code drivers from scratch but fail to see how I can map physical addresses in the first place. With other L4 kernels I would expect to find a map system call which would provide such a mapping to a thread with sufficient capabilities. In your model however, it seems that object-capabilities on such operations are transmitted to sigma0 only and that further mapping requests should go through sigma0. I actually lack any example on how to talk to sigma0 in the first place - what OC should I use as the first argument of l4sigma0_map_iomem(). - I also fail to understand the actual meaning of the environment OCs "map region" and "mem alloc" and the actual operations they provide, along with the "classic capabilities" my thread has on physical addresses for instance. Moreover, is there any configuration step where I can modify/list those "classic capabilities" passed to the thread spawned by moe? Any help/clarification would be greatly appreciated, François -- Goichon François PhD - Hardware Security in Operating Systems INSA Lyon, Dpt. Telecommunications - francois.goichon@insa-lyon.fr CITI Laboratory, INRIA - francois.goichon@inria.fr
On Tue Oct 04, 2011 at 10:29:11 +0200, François Goichon wrote:
I have some questions regarding object-capabilities and physical memory mapping.
- First of all, my goal is to manage and develop drivers on top of Fiasco. The documentation mentions the existence of an I/O server that does not seem to be on the repository anymore. Did I miss any announcement or is the I/O server in development?
It's there at l4/pkg/io
- As I did not find this server, I tried to code drivers from scratch but fail to see how I can map physical addresses in the first place. With other L4 kernels I would expect to find a map system call which would provide such a mapping to a thread with sufficient capabilities. In your model however, it seems that object-capabilities on such operations are transmitted to sigma0 only and that further mapping requests should go through sigma0. I actually lack any example on how to talk to sigma0 in the first place - what OC should I use as the first argument of l4sigma0_map_iomem().
You give it the cap to sigma0, but I won't go further, it's not supposed to be used by apps.
- I also fail to understand the actual meaning of the environment OCs "map region" and "mem alloc" and the actual operations they provide, along with the "classic capabilities" my thread has on physical addresses for instance. Moreover, is there any configuration step where I can modify/list those "classic capabilities" passed to the thread spawned by moe?
Ned is the component that loads programs and sets up their initial environment, including caps. You cannot list them, but you do know them because they are specified in the loader script. Programs generally do not know anything about physical addresses or memory. The memory allocator provides you with memory in the form of dataspaces. Those dataspaces can be mapped into an address space. For device iomem io also provides a dataspace that gives you access to the mmio region of the devices the app is assigned to. Adam -- Adam adam@os.inf.tu-dresden.de Lackorzynski http://os.inf.tu-dresden.de/~adam/
As I did not answer to the list in the first place, I'll do it again.
It's there at l4/pkg/io I used the svn checkout command provided at http://os.inf.tu-dresden.de/L4Re/download.html which apparently contains a restricted number of packages. I just saw much more packages were provided within the snapshot tarball.
You give it the cap to sigma0, but I won't go further, it's not supposed to be used by apps. Ned is the component that loads programs and sets up their initial environment, including caps. You cannot list them, but you do know them because they are specified in the loader script. Programs generally do not know anything about physical addresses or memory. The memory allocator provides you with memory in the form of dataspaces. Those dataspaces can be mapped into an address space. For device iomem io also provides a dataspace that gives you access to the mmio region of the devices the app is assigned to.
As my goal is to probably replace the standard io server implementation and to extend some kernel mechanics, I don't really want to base myself on L4re and its high level servers. I actuall want to understand and use the basic kernel mechanics. I would like to know how and where the sigma0 cap is granted to io and moe as well as some kernel interface / internal insights, if any documentation or example is available. Thank you very much for those answers, the snapshot packages are already a good starting point for me. François
Hi,
It's there at l4/pkg/io I used the svn checkout command provided at http://os.inf.tu-dresden.de/L4Re/download.html which apparently contains a restricted number of packages. I just saw much more packages were provided within the snapshot tarball.
Yes, when checking out L4Re you only get the basic set of packages. The command for checking out the IO server will then be: $> cd l4/pkg $> svn up io The full list of available subdirectories can also be obtained by running "svn ls" in the l4/pkg directory.
As my goal is to probably replace the standard io server implementation and to extend some kernel mechanics, I don't really want to base myself on L4re and its high level servers.
If you gave us more detail on what you are trying to do, we might perhaps be able to point you into the right direction. Cheers, Bjoern -- Dipl.-Inf. Bjoern Doebel Mail: doebel@tudos.org TU Dresden, OS Chair Phone: +49 351 463 38 799 Noethnitzer Str. 46 Fax: +49 351 463 38 284 01187 Dresden, Germany WWW: http://www.tudos.org/~doebel
participants (3)
-
Adam Lackorzynski -
Björn Döbel -
François Goichon