RMGR-Extension to control I/O access

[Christian Stueble]

Am Sun, 17 Oct 1999 schrieben Sie:
> Christian Stueble <stueble at amaunet.cs.uni-dortmund.de> writes:
> 
> > 
> > Hello,
> > 
> > I don´t know very much about the i386-processor and Fiasco, therefore
> > I would like to know if the following RMGR/Fiasco extensions are possible.
> > 
> > 1) As default, no task has I/O port access. (CPL > IOPL or I/O permission
> >     bitmap pointer invalid)
> > 
> > 2) A task asks via IPC the RMGR for I/O port access, e.g. port=0x80, length=4.
> > 
> > 3) The RMGR checks, if port access can be granted. If yes, the RMGR decreases   
> > the tasks CPL and/or changes the tasks I/O permission bitmap.
> > 
> > ==> Task is able to access port 0x80 - 0x83.
> > 
> > The main question: I don´t know if a task is able to change the CPL
> > or the I/O permission bitmap of another task. 
> 
> 
> That is exactly what io flex pages are designed for. Initially sigma0
> has access to all io ports and can use io flex pages to grant port
> access to other task. If sigma0 grants access a subset of the io
> address space (adressses which are accessed by in/out instructions)
> the task gets an io permission bitmap. If sigma0 (or someone else)
> grants access to the whole io address space l4 changes the iopl so
> that any thread in this task can access any port and can even disable
> interrupts.
I understand the x86 manual in that way: i/o access is permitted only if the
tasks CPL <= IOPL _and_ if appropriated bits are set to 0.
 
> 
> So the only missing feature is an implementation of io flex pages.
Generally, only two new IPC messages (to the RMGR or sigma0?) are
necessary:
1) demandPort( port_nr, size )
2) releasePort( port_nr, size )

Does someone know, why the l4 reference manual restricts the granularity of
port access to 16 byte?
 
Chris

P.S. Unfortunately this does not work with memory mapped i/o, because iopl
and permission bitmap only control in/out instructions. 
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 Christian Stueble............stueble at ls6.cs.uni-dortmund.de
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